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Silicon Photonics Technology Developments

Thursday, April 6th, 2017


By Ed Korczynski, Sr. Technical Editor

With rapidly increasing use of “Cloud” client:server computing there is motivation to find cost-savings in the Cloud hardware, which leads to R&D of improved photonics chips. Silicon photonics chips could reduce hardware costs compared to existing solutions based on indium-phosphide (InP) compound semiconductors, but only with improved devices and integration schemes. Now MIT researchers working within the US AIM Photonics program have shown important new silicon photonics properties. Meanwhile, GlobalFoundries has found a way to allow for automated passive alignment of optical fibers to silicon chips, and makes chips on 300mm silicon wafers for improved performance at lower cost.

In a recent issue of Nature Photonics, MIT researchers present “Electric field-induced second-order nonlinear optical effects in silicon waveguides.” They also report prototypes of two different silicon devices that exploit those nonlinearities: a modulator, which encodes data onto an optical beam, and a frequency doubler, a component vital to the development of lasers that can be precisely tuned to a range of different frequencies.

This work happened within the American Institute for Manufacturing Integrated Photonics (AIM Photonics) program, which brought government, industry, and academia together in R&D of photonics to better position the U.S. relative to global competition. Federal funding of $110 million was combined with some $500 million from AIM Photonics’ consortium of state and local governments, manufacturing firms, universities, community colleges, and nonprofit organizations across the country. Michael Watts, an associate professor of electrical engineering and computer science at MIT, has led the technological innovation in silicon photonics.

“Now you can build a phase modulator that is not dependent on the free-carrier effect in silicon,” says Michael Watts in an online interview. “The benefit there is that the free-carrier effect in silicon always has a phase and amplitude coupling. So whenever you change the carrier concentration, you’re changing both the phase and the amplitude of the wave that’s passing through it. With second-order nonlinearity, you break that coupling, so you can have a pure phase modulator. That’s important for a lot of applications.”

The first author on the new paper is Erman Timurdogan, who completed his PhD at MIT last year and is now at the silicon-photonics company Analog Photonics. The frequency doubler uses regions of p- and n-doped silicon arranged in regularly spaced bands perpendicular to an undoped silicon waveguide. The space between bands is tuned to a specific wavelength of light, such that a voltage across them doubles the frequency of the optical signal passing. Frequency doublers can be used as precise on-chip optical clocks and amplifiers, and as terahertz radiation sources for security applications.

GlobalFoundries’ Packaging Prowess

At the start of the AIM Photonics program in 2015, MIT researchers had demonstrated light detectors built from efficient ring resonators that they could reduce the energy cost of transmitting a bit of information down to about a picojoule, or one-tenth of what all-electronic chips require. Jagdeep Shah, a researcher at the U.S. Department of Defense’s Institute for Defense Analyses who initiated the program that sponsored the work said, “I think that the GlobalFoundries process was an industry-standard 45-nanometer design-rule process.”

The Figure shows that researchers at IBM developed an automated method to assemble twelve optical fibers to a
silicon chip while the fibers are dark, and GlobalFoundries chips can now be paired with this assembly technology. Because the micron-scale fibers must be aligned with nanometer precision, default industry standard has been to expensively align actively lit fibers. Leveraging the company’s work for Micro-Electro-Mechanical Sensors (MEMS) customers, GlobalFoundries uses an automated pick-and-place tool to push ribbons of multiple fibers into MEMS groves for the alignment. Ted Letavic, Global Foundries’ senior fellow, said the edge coupling process was in production for a telecommunications application. Silicon photonics may find first applications for very high bandwidth, mid- to long-distance transmission (30 meters to 80 kilometers), where spectral efficiency is the key driver according to Letavic.

FIGURE: GlobalFoundries chips can be combined with IBM’s automated method to assemble 12 optical fibers to a silicon photonics chip. (Source: IBM, Tymon Barwicz et al.)

GobalFoundries has now transferred its monolithic process from 200mm to 300mm-diameter silicon wafers, to achieve both cost-reduction and improved device performance. The 300mm fab lines feature higher-N.A. immersion lithography tools which provide better overlay and line width roughness (LWR). Because the of the extreme sensitivity of optical coupling to the physical geometry of light-guides, improving the patterning fidelity by nanometers can reduce transmission losses by 3X.


Tallness Makes Reliable Spindt Tip Cold Cathodes

Monday, November 30th, 2015


By Ed Korczynski, Sr. Technical Editor

MIT researchers have seemingly found a solution to a half-century-old engineering challenge:  how to make a reliable cold cathode array for vacuum electronic devices. While solid-state technology continues to replace vacuum tubes for most electronic applications—the most recent being light emitting diode (LED) luminaires replacing both incandescent and fluorescent light bulbs—there are still applications where vacuum-based devices provide unmatched performance. At the IEEE’s upcoming annual International Electron Devices Meeting (IEDM, Stephen Guerrera will present paper number 33.1 entitled “High Performance and Reliable Silicon Field Emission Arrays Enabled by Silicon Nanowire Current Limiters” on behalf of his team. Since these field emission arrays (FEA) are built in silicon, they can be integrated as cold cathodes with silicon ICs to function as compact RF amplifiers and as sources of terahertz, infrared, and X-ray energy.

Figure 1 shows a 3D illustration of the FEA structure, along with scanning electron microscope (SEM) close-up images of one tip cross-section and the tip array. The array of cold cathodes can be considered as a group of nanoscale electron guns. Each 10µm tall and 100-200nm diameter vertical silicon nanowire is topped by a 6-8nm diameter conical emitter tip.

FIGURE 1: (top) 3D schematic of the FEA device structure showing 50:1 aspect-ratio silicon nanowires, and (bottom) left-side SEM image of one tip cross-section, and right-side plan-view SEM of gate holes showing 1µm spacing and a gate aperture of 350nm.

As can be seen in the bottom left of Figure 1, the researchers used a variation on the now-standard “Bosch” deep reactive ion etch (DRIE, process to form the nanowires. The Bosch process uses vertical etching with side-wall dielectric deposition in alternating sequences such that cross-sections appear with characteristic scalloped profiles. It appears that the other unit-processes used by the MIT team to create this new device are likewise similar to industry standards.

However, while based on standard processes, the cost of using a Bosch etch and the other steps needed to fabricate the 50:1 aspect-ratio (AR) of these 200nm diameter wires is inherently high. In constrast, 5:1 AR structures can be formed using much less expensive processes, while 1:1 AR cones as used in original Spindt tips can be very inexpensive to make. Why do these nanowires need to be so tall?


Decades before organic light emitting diode (OLED) technology was to be the future of flat panel display (FPD) manufacturing, Field Effect Display ( FED) technology was explored as a more efficient replacement for liquid crystal displays (LCD). FED have typically been built using “Spindt Tip” Arrays, named after Charles A. Spindt who developed the technology for SRI International as originally published as “A thin-film field-emission cathode,” Journal of Applied Physics, vol. 39, no. 7, pages 3504-3505, 1968. Figure 2 shows how FED use multiple redundant Spindt Tips to light up the phosphor in each color sub-pixel. With ten or more connected in parallel, if one tip fails then the remaining tips in the sub-pixel cluster only have to handle a 10% increase in current…under another tip fails…and another tip will fail over time without a way to limit current.

FIGURE 2: Cross-sectional schematic of a pixel in a field effect display (FED), showing multiple redundant Spindt Tips driving a single phosphor dot.

Though inherently prone to reliability issues, the original Spindt Tip design is extraordinarily manufacturable. After layers of blanked film depositions, the top gate is patterned with uniform holes which serve as masks for both the etching of cavities and the deposition of tips. Each resulting cone-shaped tip concentrates the current to the point, allowing for efficient low voltage operation. The problem with concentrating current is that over time it tends to find a weak spot in grain boundaries resulting in decreased electrical resistance on one side of a tip, such that current flow over-concentrates and run-away heating causes the tip to fail.

In 2002 and still with SRI International, Spindt was co-author on “Spindt cathode tip processing to enhance emission stability and high-current performance” published by the American Vacuum Society [DOI: 10.1116/1.1527954]. The paper describes using the extracted field emission current to controllably heat and recrystallize the surface of Spindt tips to drive off impurities and smooth the tip surface, thereby producing more uniform physical arrays for more reliable functionality.

While alloys and anneals can improve the reliability, the run-away over-heating effect remains an inherent issue with conical tips. Dean et al. from Motorola worked on FEDs for many years, and found that individual tips emit from multiple nano-scale features with fluctuating current levels [DOI: 10.1109/IVMC.2001.939681]. It only takes one of these nano-scale features to preferentially line-up with a grain-boundary for it to draw relatively more current, and with electro-migration the feature can grow from the surface to be relatively closer to the gate compared to the rest of the tip. A protruding nano-spike create an extremely concentrated electrical field, which further concentrates the current flowing to the protrusion until it tends to physically explode.


Having exhausted all easier solutions, it now appears that using DRIE to create 50:1 AR vertical nanowires is the way to make reliable FEA. The nanowires act as current limiters to protect each emitter tip from run-away heating and arcing, and thereby design-in reliability unlike simple Spindt Tip cones. Since high-quality silicon epitaxial layers with controlled dopant levels to ensure uniform electrical resistivity can be commercially sourced, the resistance of nanowire arrays etched from such an epi-layer can be easily controlled. These device reportedly exhibit long lifetimes and low-voltage operation.

The team built emitter arrays as large as 1,000 x 1,000, and have shown ability to handle current density of >100 A/cm2, more than a hundredfold greater than any other field-emission cathode operated in continuous wave mode. These new devices combine the positive aspects of solid state semiconductors (high gain and low noise) with those of vacuum electronics (high power and efficiency). While not likely to appear in commercial FPDs, there seems to be demand for this technology in diverse communications, defense, and healthcare applications.