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Posts Tagged ‘Amkor’

Packaging Conference Addresses Challenges, Opportunities in New Technologies

Friday, December 18th, 2015

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By Jeff Dorsch, Contributing Editor

On the second day of the 12th annual 3D ASIP conference, the heavy hitters came out to talk. Attendees heard presentations from executives of Amkor Technology, the Defense Advanced Research Projects Agency (DARPA), Northrop Grumman, Taiwan Semiconductor Manufacturing, Teledyne Scientific & Imaging, and Xilinx, among other companies.

The day began with Pioneer Awards presented to Mitsumasa Koyanagi of Tohoku University and Peter Ramm of Fraunhofer EMFT. Those two men then gave talks on their involvement in 3D packaging technology over the decades.

“It started with DRAM in 1974,” Koyanagi recalled.

Ramm reviewed various European initiatives in the field, including the development of InterChip Vias (ICVs), a precursor to through-silicon via (TSV) technology, and the concept of known good die.

Suresh Ramalingam of Xilinx discussed the attributes of Silicon-less Interconnect Technology (SLIT), which the chip company developed in cooperation with Siliconware Precision Industries (SPIL), the IC assembly, bumping, and testing contractor.

“It’s still a silicon platform,” he pointed out. SLIT promises to connect multiple die in a package without resorting to TSVs. “Wafer warpage is a big issue,” Ramalingam noted.

Amkor’s Mike Kelly followed Ramalingam. “There’s a kind of upturn or resurgence in 2.5D, driven by high-bandwidth memory,” he said.

Amkor is offering the Silicon-less Interposer Module (SLIM) as its TSV alternative technology, according to Kelly, while also providing Silicon Wafer Integrated Fan-out Technology (SWIFT) as another packaging alternative to TSV-based interconnections.

KC Yee of TSMC, filling in for an absent presenter, spoke at length about the foundry’s Integrated Fan-Out (InFO) wafer-level packaging technology. “InFO eliminates silicon, TSVs, interposers,” he said. At the same time, InFO “reduces cost,” he asserted.

DARPA’s Daniel Green spoke about the agency’s Diverse Accessible Heterogeneous Integration (DAHI) program, which succeeded its Compound Semiconductor Materials on Silicon (COSMOS) program.

He was followed by Augusto Gutierrez-Aitken of Northrop Grumman Aerospace Systems. “DAHI is not in competition with CMOS,” he said. NGAS is developing a foundry for heterogeneous integration projects, inviting in companies and universities to participate in the research and development.

Teledyne Scientific’s Miguel Urteaga spoke about his company’s CS-STACK 3D stacking chip program. “We’re looking to get the highest III-V performance we can,” he said.

InvenSense Developers Conference Tackles Sensor Security, New Technologies

Monday, November 23rd, 2015

By Jeff Dorsch, Contributing Editor

The second day of the InvenSense Developers Conference saw presenters get down to cases – use cases for sensors.

There were track sessions devoted to mobile technology and the Internet of Things, with the latter featuring presentations on industrial and automotive applications, smart homes and drones, smartphones and tablet computers, and wearable electronics. InvenSense partner companies had their own track on New Technologies, fitting into the conference’s “Internet of Sensors” theme.

The conference also featured two developer tracks in parallel, providing five InvenSense presentations on its FireFly hardware and software, SensorStudio, and other offerings.

One of the presentations that wrapped up the conference on Wednesday afternoon (November 18) was given by Pim Tuyls, chief executive officer of Intrinsic-ID, the Dutch company that worked with InvenSense to develop the TrustedSensor product, a secure sensor-based authentication system incorporating the FireFly system-on-a-chip device.

TrustedSensor will be shipped to alpha customers in the first quarter of 2016 and will go out to beta customers in the second quarter of next year, according to Tuyls. “This is real,” he said.

The Intrinsic-ID founder briefly reviewed the company’s history, to start. It was spun out of Royal Philips in 2008 and is an independent company with venture-capital funding, Tuyls noted.

Intrinsic-ID was founded to provide “cyber physical security based on physically unclonable function,” or PUF, Tuyls said. “We invented PUF,” he added. “It has been vetted by security labs and government agencies,” among other parties.

Taking “The Trusted Sensor” as his theme, the Intrinsic-ID CEO said, “Sensors are the first line of defense. You want to make sure you can provide a certain level of security.”

It is critical to achieve “the right balance” in designing, fabricating, and installing sensors, with security, flexibility, and low footprint among the key considerations, according to Tuyls.

While whimsically describing PUF as “a magic concept,” Tuyls noted, “Chips are physically unique,” with no two completely alike due to manufacturing processes.

PUF can “extract a crypto key from any device,” he added. “You can authenticate any device.”

Intrinsic-ID has tested the PUF technology with a wide variety of silicon foundries, Tuyls said – namely, Cypress Semiconductor, GlobalFoundries, IBM, Intel, Renesas Electronics, Samsung Electronics, Taiwan Semiconductor Manufacturing, and United Microelectronics. It has been implemented by Altera, Microsemi, NXP Semiconductors, Samsung, and Synopsys, he added, and process nodes ranging from 180 nanometers down to 14nm have been tested.

Tuyls concluded by emphasizing the importance of sensor security for the Internet of Things. “We should not wait; we should not try to save a few cents,” he said. “It is important, but it is hard.”

Earlier in the day, attendees heard from Sam Massih, InvenSense’s director of wearable sensors. “There’s a wearable solution for every part of the body,” he commented.

“Step count isn’t enough,” Massih said. “You need context for data.” He cited the example of a user who goes to the gym three times a week and spends an hour on the elliptical trainer machine for one hour on each visit.

“That’s data that can be monetized,” he said.

InvenSense announced last month that it would enter the market for automotive sensors. Amir Panush, the company’s head of automotive and IoT industrial, said in his presentation, “Sensors need to be smart enough.”

The megatrends in automotive electronics include the use of motion sensors for safety in advanced driver-assistance systems (ADAS), the smart connected car, and tough emission restrictions, according to Panush.

“We have signed a deal with a Tier One partner,” Panush said, meaning a leading automotive manufacturer, without identifying the company. “We are ramping up internal R&D in automotive.” InvenSense is presently opening design centers focusing on the $5 trillion automotive market, he added.

InvenSense was founded in 2003 and went public in 2011. The company posted revenue of $372 million in fiscal 2015 with a net loss of $1.08 million (primarily due to charging $10.55 million in interest expense against net income), after being profitable for the previous four years. InvenSense gets more than three-quarters of its revenue from mobile sensors and has a growing business in IoT sensors.

Customers in Asia accounted for 63 percent of the company’s fiscal 2015 revenue, according to InvenSense’s 10-K annual report. The company spent $90.6 million on research and development, representing about 24 percent of its net revenue.

GlobalFoundries and TSMC make nearly all of InvenSense’s wafers. Assembly packaging of its microelectromechanical system (MEMS) devices and sensors is outsourced to Advanced Semiconductor Engineering, Amkor Technology, Lingsen Precision Industries, and Siliconware Precision Industries.

The company had 644 employees as of March 29, 2015, with nearly half of them involved in R&D.

STMicroelectronics is InvenSense’s primary competitor for consumer motion sensors, the 10-K states, while the company also competes with Analog Devices, Epson Toyocom, Kionix, Knowles, Maxim Integrated Products, MEMSIC, Murata Manufacturing, Panasonic, Robert Bosch, and Sony.

Solid State Watch: July 17-23, 2015

Friday, July 24th, 2015
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Blog review December 16, 2014

Tuesday, December 16th, 2014

Maybe, just maybe, ASML Holding N.V. (ASML) has made the near-impossible a reality by creating a cost-effective Extreme Ultra-Violet (EUV @ ~13.5nm wavelength) all-reflective lithographic tool. The company has announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has ordered two NXE:3350B EUV systems for delivery in 2015 with the intention to use those systems in production. In addition, two NXE:3300B systems already delivered to TSMC will be upgraded to NXE:3350B performance. While costs and throughputs are conspicuously not-mentioned, this is still an important step for the industry.

The good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2014 IEEE International Electron Devices Meeting. Dick James of Chipworks writes that it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

The 4th Annual Global Interposer Technology Workshop at GaTech gathered 200 attendees from 11 countries to discuss the status of interposer technology. It has become the one meeting where you can find all the key interposer layers including those representing glass, laminate and silicon, blogs Phil Garrou.

Sharon C. Glotzer and Nicholas A. Kotov are both researchers at the University of Michigan who were just awarded a MRS Medal at the Materials Research Society (MRS) Fall Meeting in San Francisco for their work on “Integration of Computation and Experiment for Discovery and Design of Nanoparticle Self-Assembly.”

In order to keep pace with Moore’s Law, semiconductor market leaders have had to adopt increasingly challenging technology roadmaps, which are leading to new demands on electronic materials (EM) product quality for leading-edge chip manufacturing. Dr. Atul Athalye, Head of Technology, Linde Electronics, discusses the challenges.

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. Adele Hars reports.

Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.

At the recent IMAPS conference, Samsung electro-mechanics compared their Plated Mold Via Technology (PMV) to the well known Amkor Through Mold Via  (TMV) technology. The two process flows are compared. Phil Garrou reports.

The Week in Review: August 22, 2014

Friday, August 22nd, 2014

Himax Technologies, Inc., a supplier and fabless manufacturer of display drivers and other semiconductor products, and Lumus, a producer of Augmented Reality glasses, announced another joint initiative to continue developing the next-generation of smart glasses that will set new technological standards in image quality and performance.

North America-based manufacturers of semiconductor equipment posted $1.41 billion in orders worldwide in July 2014 (three-month average basis) and a book-to-bill ratio of 1.07, according to the July EMDS Book-to-Bill Report published this week by SEMI.   A book-to-bill of 1.07 means that $107 worth of orders were received for every $100 of product billed for the month.

Intel Corporation and Unity Technologies this week announced a strategic collaboration to advance the development of Android-based applications on Intel architecture. The agreement accelerates Intel’s mobility push as millions of developers using the Unity development platform can now bring native Android games and other apps to Intel-based mobile devices. Unity adds support for Android across all of Intel’s current and future processors including both the Intel Core and Intel Atom processor families.

MediaTek this week announced the establishment of a new research and development facility in Bengaluru, India. The new R&D facility will focus on developing innovative and inclusive solutions for wireless communications and establish MediaTek’s presence in other core segments such as connectivity and home entertainment devices.

Amkor Technology, Inc. announced that David Watson has been appointed as a new member of the Company’s Board of Directors. With this appointment, Amkor’s Board has been expanded to nine members. Mr. Watson is currently serving as Executive Vice President and Chief Operating Officer for Comcast Cable. In this role Mr. Watson oversees the teams responsible for day-to-day operations of the cable division, including sales and marketing of cable video, high-speed Internet and voice services, as well as oversight of the three operating divisions and Comcast Spotlight, the advertising sales unit.

STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, announced this week that it has shipped over 100 million semiconductor packages with the company’s fcCuBE technology, advanced flip chip packaging with fine pitch copper (Cu) column bumps, Bond-on-Lead (BOL) interconnection and enhanced assembly processes.

Intersil Corporation, a provider of power management and precision analog solutions, announced the ISL98611 display power and LED driver for smartphones. The ISL98611 is the first power management IC that integrates the display power and backlight LED driver functions in a single chip. It significantly improves efficiency of both functions to increase smartphone battery life by an hour or more.

Wafer-level packaging of ICs for mobile systems of the future

Monday, May 5th, 2014

Ed Korczynski, Senior Technical Editor, Solid State Technology/SemiMD

The most functionality at the least cost is the promise of wafer-level packaging (WLP) when dealing with complex integrated circuits (IC) with a high number of input/output connections to the outside world. Integration of heterogeneous circuit functions—such as micro- and graphics-processing, field-programmable gate array (FPGA) logic, dynamic and static memory, radio-frequency (RF) and analog, and sensing and actuating—may also be needed at the package-level to be able to deliver complete systems (Figure 1).

FIGURE 1: Heterogeneous System-in-Package (SiP) as an extension of proven flip-chip (FC) packaging technology. (Source: Amkor)

In particular, electronic systems for high-growth mobile applications require low-power and low-volume per element which dis-allows circuit integration at the printed-circuit board (PCB) level. Instead, heterogeneous integration must occur as either a system-in-package (SIP) or a system on-chip (SOC). Dr. Eric Mounier of Yole Développement, presented at the recent European 3D TSV Summit 2014 held in Grenoble, and showed Yole forecasts that total world-wide semiconductor IC wafers packaged at the wafer-scale will be 19% this year, raising to 20% in 2015.

One way of looking at the history of the IC industry is to examine the dynamic between SIP and SOC approaches. New functionalities tend to be first integrated into hardware as dedicated additional chips, to be connected in to the rest of the system as part of a PCB or SIP. Since different functionalities often require different fab processes, it is generally less expensive at the chip-level to divide functionalities into different chips, but then the packaging costs tend to be higher. Relatively low-volume parts may be most economically delivered as SIP, while higher-volume parts can often justify the additional design and test expenses of delivering the same functionality as a single SOC.

The other major reason to go with an SIP is to improve the yield of large area chips at the leading edge of fab processing. Since defects/area tend to be relatively high with a new fab process, very large chip designs will have relatively low yield at first but then will improve as the fab learns how to reduce both random and systematic yield limiters. The recent excellent example of this trend is the Xilinx Vertex-7 FPGA which splits the chip into four sub-chips and then uses a silicon interposer for SIP re-integration. We may expect that a next-generation of the product would be build in a single SOC after the yield improves, at which point Xilinx would be expected to extend the product line with additional functionality added in using multi-chip SIP.

Fan-Out WLP

Steffen Kroehnert, director of technology for Nanium S.A., gave a recent presentation at SEMICON/Singapore 2014 entitled “Wafer Level Fan-Out as Fine-Pitch Interposer.” Fan-In WLP uses layout package connections within the chip area, and when the scale and count of on-chip bond pads does not match with standard packaging scales, a Re-Distribution Layer (RDL) of metal interconnect  can be used to Fan-In to ball-grid or pillar-grid arrays (BGA/PGA) within the chip-area. However, when the needed number of connections cannot be made within the chip area, packaging filler materials can be used to provide physical area adjacent to an original chip such that package connections can be arranged to Fan-Out WLP solutions use “Fan-Out” out from the chip center when seen from above.

Chip-Package-Board simultaneous co-design and co-development are becoming import instead of serial work according to Kroehnert. The penalty for re-design costs and losing strategic time-to-market for a new SiP is too high for allow for iterative R&D, such that products must be co-designed properly the first time.

FO-WLP Leveraging PV Fab Tricks

Deca Technologies, the electronic interconnect solutions provider to the semiconductor industry owned by Cypress Semiconductor, recently announced that it has shipped its 100-millionth component. The company attributes this milestone to strong demand from portable electronics manufacturers for wafer-level chip scale packages (WLCSP) manufactured using Deca’s unique, integrated Autoline production platform, which is designed to achieve faster time-to-market at lower cost.

Leveraging volume production technologies from leading silicon PV manufacturer SunPower Corp., Deca quickly achieved this milestone by addressing cycle time and capital cost challenges that semiconductor device manufacturers have struggled with using conventional approaches to WLCSP manufacturing. Deca claims that other FO-WLP technologies suffer from inherent manufacturing and reliability issues due to discontinuity at the silicon:mold-compound interface, which are avoided by the company’s use of copper-pillars and an over-mold approach (Figure 2).

FIGURE 2: Cross-section of edge of FO-WLP using Cu-pillars and over-mold approach. (Source: Deca Technologies)

Demand for WLCSP is being driven by manufacturers of wireless connectivity, audio, and power management components for mobile markets. Demand fluctuations in these markets can lead to challenges in managing inventories. “Congratulations to the Deca team on achieving this significant milestone,” said Brent Wilson, senior vice president of the Global Supply Chain Organization at ON Semiconductor. “Deca’s innovative technologies and focus on customer service have made the company a valuable part of our supply chain.”

“Reaching 100 million units is an important milestone for Deca because it validates our unique approach to WLCSP manufacturing,” said Chris Seams, CEO of Deca Technologies. “Based on the demand forecasted by our customers, we anticipate passing the half-billion mark in unit shipments this year.”

FO-WLP for the future

As thoroughly covered in our sister blog Insights From The Leading Edge, STATSChipPAC (SCP) recently announced FlexLine™ FO-WLP. The FlexLine flow dices and reconstitutes incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size. The SCP FlexLine process flow is based on the SCP commercial eWLB FO-WLP process (Figure 3). Single and multi die fan-out package solutions have been in high-volume manufacturing since 2009 with more than a half-billion units shipped.

FIGURE 3: Schematic cross-sections of various Fan-Out WLP packages. (Source: STATSChipPAC)

Earlier this month, Digitimes provided a brief English translation of some Chinese-language Economic Daily News (EDN) saying that Taiwan Semiconductor Manufacturing Company (TSMC) plans to increase IC packaging revenues to US$1 billion in 2015 and to US$2 billion in 2016. TSMC co-CEO CC Wei reportedly acknowledged that the production cost for silicon-substrate SIP (TSMC’s variant termed “chip-on-wafer-on-substrate” or “CoWoS”) packages is relatively high, and so the world’s leading IC foundry intends to invest in FO-WLP technologies to be able to offer advanced packaging at a reduced price.

Wafer-level packaging continues to gain slow IC market share, and novel fan-out redistribution drives the need for improvements in existing packaging materials within tight cost and reliability constraints. With silicon-interposers and copper-interconnects part of WLP technology, the lines between chip and package have never been less clear. Managing all of this complexity is business as usual when designing mobile systems of the future.

‒E.K.

Blog review April 22, 2014

Tuesday, April 22nd, 2014

Pete Singer blogs that it’s difficult to make interconnects much smaller without introducing significant increases in resistivity. At the upcoming IITC/AMC joint conference in May, many papers focus on new materials that could lead to reduced resistivity and enable further interconnect scaling. Most notably, graphene and CNTs provide an interesting alternative to copper.

Phil Garrou continues his analysis of the IMAPS Device Packaging Conference with a look at the presentations made by Flip Chip International and SUSS (the use of lasers in the manufacturing of WLP); GLOBALFOUNDRIES, Amkor and Open Silicon (a 2.5D ARM dual core product demonstrator which consists of 2 ARM die on a high density silicon interposer); Corning (results of multiple glass interposer programs) and Namics (underfill products for FC BGA and FC CSP).

Blog review February 10, 2014

Monday, February 10th, 2014

Dick James of ChipWorks blogs that when Intel launched their Haswell series chips last June, they stated that the high-end systems would have embedded DRAM, as a separate chip in the package. “It took us a while to track down a couple of laptops with the requisite Haswell version, but we did and now we have a few images that show it’s a very different structure from the other e-DRAMs that we’ve seen,” he notes.

Phil Garrou continues his look at the 2013 Georgia Tech Interposer Conference, focusing on presentations from Amkor and GlobalFoundries. He writes that Ron Huemoeller of Amkor projects that in the high end silicon will dominate; in the mid-end, silicon will be prominent and organic /glass may play a role; in the low end, organic, or low cost glass or silicon if they exist will play a role. Dave McCann of GlobalFoundries examined market needs for interposers.

Semico’s review of the latest and greatest from the Consumer Electronics Show highlights five technologies they think you should pay attention to as game changers: 3D Printing, the Bosch wireless sensor network for IoT; Bionics: Thought-controlled prosthetics; Aging in place: Pain relief; and LED Lighting.

Vivek Bakshi, of EUV Litho, Inc., ponders some interesting questions, such as how important is the semiconductor industry relative to other industries, and how did we get to where we are, the continuation of Moore’s Law and why have there been so few Nobel prizes given to the chip industry?

Karen Lightman of the MEMS Industry Group says the upcoming MEMS Executive Congress Europe “checks all the boxes” with great content and speakers, networking time with MEMS industry execs and OEM users, and an unbeatable location in Munich.

Pete Singer takes a look back at February 1964 through the pages of Solid State Technology, when wafers were small, dreams were big and The Beatles were on the Ed Sullivan show. The issue discussed thermionic energy convertors, the potential of which is still being explored today by Stanford.

Blog Review: December 2, 2013

Monday, December 2nd, 2013

Phil Garrou completes his look at various packaging and 3D integration happenings from Semicon Taiwan, including news from Disco, Namics and Amkor. Choon Lee of Amkor, for example, predicted a silicon interposer cost of 2.7-4$/cm sq (100 sq mm) and expectations of organic interposer costs at 50% cost reduction.

Dynamic resource allocation can significantly improve turnaround time in post-tapeout flow. Mark Simmons of Mentor Graphics blogs about recent work that demonstrated 30% aggregate turnaround time improvement for a large set of jobs in conjunction with a greater than 90% average utilization across all hardware resources.

The MEMS Industry Group blog reflects on the trend toward sensor fusion and the role that hardware approaches such as FPGAs and microcontrollers will play in moving the technology forward.

44 years ago, the internet was born when two computers, one at UCLA and one at the Stanford Research Institute, connected over ARPANET (Advanced Research Projects Agency Network) to exchange the world’s first “host-to-host” message. Ricky Gradwohl of Applied Materials celebrates the “birthday” with thoughts on how far the internet has come.