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Posts Tagged ‘ALE’

Mechanistic Modeling of Silicon ALE for FinFETs

Tuesday, April 25th, 2017

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With billions of device features on the most advanced silicon CMOS ICs, the industry needs to be able to precisely etch atomic-scale features without over-etching. Atomic layer etching (ALE), can ideally remove uniform layers of material with consistent thickness in each cycle, and can improve uniformity, reduce damage, increase selectivity, and minimize aspect ratio dependent etching (ARDE) rates. Researchers Chad Huard et al. from the University of Michigan and Lam Research recently published “Atomic layer etching of 3D structures in silicon: Self-limiting and nonideal reactions” in the latest issue of the Journal of Vacuum Science & Technology A (http://dx.doi.org/10.1116/1.4979661). Proper control of sub-cycle pulse times is the key to preventing gas mixing that can degrade the fidelity of ALE.

The authors modeled non-idealities in the ALE of silicon using Ar/Cl2 plasmas:  passivation using Ar/Cl2 plasma resulting in a single layer of SiClx, followed by Ar-ion bombardment to remove the single passivated layer. Un-surprisingly, they found that ideal ALE requires self-limited processes during both steps. Decoupling passivation and etching allows for several advantages over continuous etching, including more ideal etch profiles, high selectivity, and low plasma-induced damage. Any continuous etching —when either or both process steps are not fully self-limited— can cause ARDE and surface roughness.

The gate etch in a finFET process requires that 3D corners be accurately resolved to maintain a uniform gate length along the height of the fin. In so doing, the roughness of the etch surface and the exact etch depth per cycle (EPC) are not as critical as the ability of ALE to be resistant to ARDE. The Figure shows that the geometry modeled was a periodic array of vertical crystalline silicon fins, each 10nm wide and 42nm high, set at a pitch of 42 nm. For continuous etching (a-c), simulations used a 70/30 mix of Ar/Cl gas and RF bias of 30V. Just before the etch-front touches the underlying SiO2 (a), the profile has tapered away from the trench sidewalls and the etch-front shows some micro-trenching produced by ions (or hot neutrals) specularly reflected from the tapered sidewalls. After a 25% over-etch (b), a significant amount of Si remains in the corners and on the sides of the fins. Even after an over-etch of 100% (c), Si still remains in the corners.

FIGURE CAPTION: Simulated profiles resulting from etching finFET gates with (a)–(c) a continuous etching process, or (d)–(f) an optimized ALE process. Time increases from left to right, and images represent equal over-etch (as a percentage of the time required to expose the bottom SiO2) not equal etch times. Times listed for the ALE process in (d)–(f) represent plasma-on, ignoring any purge or dwell times. (Source: J. Vac. Sci. Technol. A, Vol. 35, No. 3, May/Jun 2017)

In comparison, the ALE process (d-f) shows that after 25% over-etch (e) the bottom SiO2 surface would be almost completely cleared with minimal corner residues, and continuing to 100% over-etch results in little change to the profile. The ALE process times shown here do not include the gas purge and fill times between plasma pulses; to clear the feature using ALE required 200 pulses and assuming 5 seconds of purge time between each pulse results in a total process time of 15–20 min to clear the feature. This is a significant increase in total process time over the continuous etch (2 min).

One conclusion of this ALE modeling is that even small deviations from perfectly self-limited reactions significantly compromise the ideality of the ALE process. For example, having as little as 10 ppm Cl2 residual gas in the chamber during the ion bombardment phase produced non-idealities in the ALE. Introducing any source of continuous chemical etching into the ALE process leads to the onset of ARDE and roughening of the etch front. These trends have significant implications for both the design of specialized ALE chambers, and also for the use of ALE to control uniformity.

—E.K.

Applied Materials Releases Selective Etch Tool

Wednesday, June 29th, 2016

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By Ed Korczynski, Sr. Technical Editor

Applied Materials has disclosed commercial availability of new Selectra(TM) selective etch twin-chamber hardware for the company’s high-volume manufacturing (HVM) Producer® platform. Using standard fluorine and chlorine gases already used in traditional Reactive Ion Etch (RIE) chambers, this new tool provides atomic-level precision in the selective removal of materials in 3D devices structures increasingly used for the most advanced silicon ICs. The tool is already in use at three customer fabs for finFET logic HVM, and at two memory fab customers, with a total of >350 chambers planned to have been shipped to many customers by the end of 2016.

Figure 1 shows a simplified cross-sectional schematic of the Selectra chamber, where the dashed white line indicates some manner of screening functionality so that “Ions are blocked, chemistry passes through” according to the company. In an exclusive interview with Solid State Technology, company representative refused to disclose any hardware details. “We are using typical chemistries that are used in the industry,” explained Ajay Bhatnagar, managing director of Selective Removal Products for Applied Materials. “If there are specific new applications needed than we can use new chemistry. We have a lot of IP on how we filter ions and how we allow radicals to combine on the wafer to create selectivity.”

FIG 1: Simplified cross-sectional schematic of a silicon wafer being etched by the neutral radicals downstream of the plasma in the Selectra chamber. (Source: Applied Materials)

From first principles we can assume that the ion filtering is accomplished with some manner of electrically-grounded metal screen. This etch technology accomplishes similar process results to Atomic Layer Etch (ALE) systems sold by Lam, while avoiding the need for specialized self-limiting chemistries and the accompanying chamber throughput reductions associated with pulse-purge process recipes.

“What we are doing is being able to control the amount of radicals coming to the wafer surface and controlling the removal rates very uniformly across the wafer surface,” asserted Bhatnagar. “If you have this level of atomic control then you don’t need the self-limiting capability. Most of our customers are controlling process with time, so we don’t need to use self-limiting chemistry.” Applied Materials claims that this allows the Selectra tool to have higher relative productivity compared to an ALE tool.

Due to the intrinsic 2D resolutions limits of optical lithography, leading IC fabs now use multi-patterning (MP) litho flows where sacrificial thin-films must be removed to create the final desired layout. Due to litho limits and CMOS device scaling limits, 2D logic transistors are being replaced by 3D finFETs and eventually Gate-All-Around (GAA) horizontal nanowires (NW). Due to dielectric leakage at the atomic scale, 2D NAND memory is being replaced by 3D-NAND stacks. All of these advanced IC fab processes require the removal of atomic-scale materials with extreme selectivity to remaining materials, so the Selectra chamber is expected to be a future work-horse for the industry.

When the industry moves to GAA-NW transistors, alternating layers of Si and SiGe will be grown on the wafer surface, 2D patterned into fins, and then the sacrificial SiGe must be selectively etched to form 3D arrays of NW. Figure 2 shows the SiGe etched from alternating Si/SiGe stacks using a Selectra tool, with sharp Si corners after etch indicating excellent selectivity.

FIG 2: SEM cross-section showing excellent etch of SiGe within alternating Si/SiGe layers, as will be needed for Gate-All-Around (GAA) horizontal NanoWire (NW) transistor formation. (Source: Applied Materials)

“One of the fundamental differences between this system and old downstream plasma ashers, is that it was designed to provide extreme selectivity to different materials,” said Matt Cogorno, global product manager of Selective Removal Products for Applied Materials. “With this system we can provide silicon to titanium-nitride selectivity at 5000:1, or silicon to silicon-nitride selectivity at 2000:1. This is accomplished with the unique hardware architecture in the chamber combined with how we mix the chemistries. Also, there is no polymer formation in the etch process, so after etching there are no additional processing issues with the need for ashing and/or a wet-etch step to remove polymers.”

Systems can also be used to provide dry cleaning and surface-preparation due to the extreme selectivity and damage-free material removal.  “You can control the removal rates,” explained Cogorno. “You don’t have ions on the wafer, but you can modulate the number of radicals coming down.” For HVM of ICs with atomic-scale device structures, this new tool can widen process windows and reduce costs compared to both dry RIE and wet etching.

—E.K.

Atomic Layer Etch now in Fab Evaluations

Monday, August 4th, 2014

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By Ed Korczynski, Sr. Technical Editor

Atomic-Layer Etch (ALE) technology from Lam Research Corp. is now in beta-site evaluations with IC fabrication (fab) customers pursuing next generation manufacturing capabilities. So said Dr. David Hemker, Lam’s senior vice president and chief technical officer, in an exclusive interview with Solid State Technology and SemiMD during this year’s SEMICON West trade-show in San Francisco. Hemker discussed the reasons why ALE is now under evaluation as a critically enabling technology for next generation IC manufacturing, and forecast widespread adoption in the industry by 2017.

As detailed in the feature article “Moving atomic layer etch from lab to fab” in last December’s issue of Solid State Technology, ALE can be plasma enhanced with minor modifications to a continuous plasma etch chamber. The lab aspects including the science behind the process were discussed in a TechXPOT during SEMICON West this year in a presentation titled “Plasma Etch in the Era of Atomic Scale Fidelity” by Lam’s Thorsten Lill based on work done in collaboration with KU Leuven and imec. In that presentation, Lill reminded the attendees that the process has been explored in labs under a wide variety of names:  ALET, atomistic etching, digital etch, layer-by-layer etch, PALE, PE-ALE, single layer etch, and thin layer etching.

ALE can be seen as a logic counter-part to atomic-layer deposition (ALD), with the commonality that both processes become cost-effective when the amount of material being either added or removed are readily measured in atomic layers. It’s comforting that when the industry needs control to the atomic-level we are dealing with such tiny structures that ALD and ALE can provide acceptable throughputs. “By 2017, we see able 15% of the opportunity for us could be addressed by atomic processing,” projected Hemker.

However, ALE as promoted by Lam differs from ALD, because etch processes generally need directionality. “That’s where it diverges from ALD,” explained Hemker. “Using ions we get all the benefits of directionality and selectivity. Likewise, if we design the process correctly, we could theoretically have infinite selectivity with under layers.” Figure 1 shows a trench formed in single-crystal silicon using ALE, with vertical side-walls and a bottom surface smooth at the atomic scale. Such process capability is based on the pulsing of both energy and chemistry into the reaction chamber.

Fig. 1: (Left) Schematic cross-section of Atomic-Layer Etch (ALE) of silicon using a silicon-oxide top mask, (Middle) SEM cross-section of nominal 40-nm silicon trench, and (Right) TEM close-up of the silicon surface showing atomic-scale smoothness.

“We need to be able to pulse multiple things at the same time,” explained Hemker. “So we can absorb a reactant, and then switch over to a plasma. The breakthrough in this is being able to pulse everything correctly.” Labs have been doing this but on a timescale of minutes per atomic layer removed. Lam productized the principle to run on a time-scale of seconds on the 2300 Kiyo tool, which is the current leading-edge hardware for conductor etch from the company.

Pulsing of energy into a reaction chamber has been used in the company’s high aspect-ratio etch process for 3D NAND which runs on the 2300 Flex tool for dielectrics. In this process flow, vias through alternating layers of oxide and nitride in a stack must be etched at 40:1 aspect-ratio today, with 60:1 and even 100:1 aspect-ratio specifications from Samsung for device evaluations. “You see it coming in with pulsing the plasma, allowing us to get ions in and reactants out,” explained Hemker. So the ALE process can be seen as an extension of this pulsing plasma approach, with the extra sophistication of pulsing the chemical precursors into the chamber. “The trick is how to do it repeatably and reliably so that it’s production worthy,” reminded Hemker.

When the ALE precursor adsorbs as a single-layer on surfaces, the connection to the surface could be merely van der Waals forces, or depending upon the application could include some reaction with underlying atoms. “The process conditions have to tailored for flows and gases, but it does open up the possibility of using less expensive process gases. There’s no new gases needed,” declared Hemker. “The real message is not that this is just a new process, but this shares a common background with ALD in pulsing things and having sophisticated enough control of the process.”

Such commonalities would seemingly extend to some chamber hardware and the vacuum and effluent abatement systems, such that it would be very straightforward to cluster single-wafer processing chambers for ALD with ALE with plasma pre-treat and possibly even with annealing. Such a cluster would allow for sophisticated “dep/etch” recipes to be developed for atomic-scale device fabrication.

Fig. 2: Commonality in the need for ALD and ALE process technologies when IC device dimensions scale to atomic levels.

Figure 2 shows the comparison between ALD and ALE processes for a trench structure, and why both are needed when device geometries reach atomic-scales. When trench aspect ratios (AR) are ~1:1 continuous deposition and etch processes can be fairly easily developed to provide uniform results. However, as the AR increases, reaction byproducts tend to non-uniformly deposit on sidewalls and especially at the corners of structures. Eventually, the top of high AR trenches “pinch-off” to create an open in IC circuitry, even when slowing down continuous processes to allow more time for byproducts to escape reaction areas.

Lam expects ALE to be used on the leading-edge of IC manufacturing within a few years, with increasing applications as more critical layers in a device must be patterned to smaller than 22nm half-pitch. “It’s not that you can’t do some of these processes with continuous etch, but ALE really opens up the process window,” explained Hemker. Now is the time for ALE, since the minimum variability of continuous etching consumes more and more of the critical dimension with ever smaller feature sizes.

“If you look at ALD as the for-runner of this, it was first adopted for capacitor deposition in a batch process, then it migrated to single-wafer for high-k metal-gate formation where greater control was needed,” reminded Hemker. “It was used but somewhat niche, and now we’re seeing traction on ALD for many more applications such as quadruple-patterning. The spacers themselves have to be perfectly conformal, because any thickness variation will be a CD variation and it compounds with quadruple patterning.”

Control of pattern fidelity at the atomic-scale will be needed as the commercial IC fab industry integrates new materials for improved device functionalities. ALE and other technologies that can control processing of individual atomic layers should be used to pattern ICs for the indefinite future.