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Posts Tagged ‘AFS’

TSMC Certifies Mentor Graphics Tools for Early Design Start in TSMC’s 10nm FinFET Technology

Monday, April 6th, 2015

Mentor Graphics Corp. (NASDAQ: MENT) announced that TSMC and Mentor Graphics have reached the first milestone of their collaboration on 10nm EDA certification. Calibre® physical verification and design for manufacturing (DFM) platform, and the Analog FastSPICE™ (AFS™) Circuit Verification Platform, including AFS Mega, are certified by TSMC based on the most current version of 10nm design rules and SPICE models.  New tool feature enhancement based on 10nm process requirements has been made in Olympus-SoC™ digital design platform with TSMC validation, and certification of full chip integration is actively on-going. In addition to 10nm, Mentor has also completed 16FF+ version 1.0 certification of the Calibre, Olympus-SoC and AFS platforms. These certifications provide designers with the earliest access to signoff technology optimized for TSMC’s most advanced process nodes, with improved performance and accuracy.

“The long-term partnership we have with Mentor Graphics enables us to work closely from the earliest phases of technology development so we can have production ready design kits and software available for our customers concurrently with the announcement of new process offerings,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “Mentor’s design solutions have successfully met the accuracy and compatibility requirements for TSMC 10nm FinFET technology, so customers can initiate their designs with accurate verification solutions.”

The Analog FastSPICE Platform provides fast circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. For large circuits the AFS Platform also delivers high capacity and fast mixed-signal simulation. For embedded SRAM and other array-based circuits, AFS Mega delivers highly accurate simulation results.

As circuit reliability remains a focus, Mentor and TSMC have enhanced the Calibre PERC™ product offering in 10nm to ensure that design and IP development teams have robust verification solutions for identifying sources of electrical error. Additionally, the Calibre xACT™ extraction suite includes updated models to deliver more accurate results to fulfill tighter accuracy requirements of 10nm.

For TSMC’s 16FF+ 1.0 Calibre design kit release, the Calibre team has worked with TSMC to speed up DRC performance by 30% on average. In addition, TSMC and Mentor released new filling use models that will improve first-pass fill runs, making ECO changes easier and faster. The new fill methodology will also help ensure consistent cycle times during post fill verification.

“Because Mentor and TSMC work together from the earliest stages of design rule development for a new process node, we learn what the new design and verification challenges are right along with TSMC.” said Joseph Sawicki, vice president and general manager of the Design to Silicon division at Mentor Graphics. “This gives us the ability to have the most advanced capabilities in place for ecosystem early adopters, and to continue to optimize performance as the new process moves to full production status.”