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Posts Tagged ‘450mm’

Blog review July 21, 2014

Monday, July 21st, 2014

Matthew Hogan, a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, blogs that SoC Reliability Verification Doesn’t Just Happen, You Know. He says the best way to verify multi-IP, multiple power domain SoCs, is with the Unified Power Format (UPF), which enables a repeatable, comprehensive, and efficient design verification methodology, using industry standards, at the transistor level.

Dick James, Senior Technology Analyst, Chipworks, has a TSMC-fabbed 20-nm part in-house, and is looking forward to the analysis results. Wondering what changes TSMC has made from the 28-nm process, Dick says he expects mostly a shrink of the latter process, with no change to the materials of the high-k stack, though maybe to the sequence.

Ed Korczynski continues his theme of “Moore’s Law is Dead” with a third installment that looks at when that might happen. He says that at ~4nm pitch we run out of room “at the bottom,” after patterning costs explode at 45nm pitch.

Vivek Bakshi, EUV Litho, Inc. blogs about The 2014 EUVL Workshop which was held late last month amid some positive highlights and lots of R&D updates. The keynote talks this year were from Intel, Gigaphoton and Toshiba.

In his 201st Insights from The Leading Edge (IFTLE) blog post, Phil Garrou takes a look at some of the presentations at this year’s ConFab. Subramani Kengeri, Vice President, Advanced Technology Architecture for GlobalFoundries discussed the techno-economics of the semiconductor industry. Gary Patton, VP of IBM Semiconductor Research & Development Center addressed “Semiconductor Technology: Trends, Challenges, & Opportunities.” Adrian Maynes, 450C program manager, discussed the “450mm Transition Toward Sustainability: Facility & Infrastructure Requirements.”

Zvi Or-Bach, President and CEO of MonolithIC 3D Inc., blogs that over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.

Blog review February 24, 2014

Monday, February 24th, 2014

Paul Farrar, general manager of the G450C consortium, said early work has demonstrated good results and that he sees no real barriers to implementing 450mm wafers from a technical standpoint. But as Pete Singer blogs, he also said: “In the end, if this isn’t cheaper, no one is going to do it,” he said.

Adele Hars of Advanced Substrate News reports that body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages.

Dr. Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering, ProPlus Design Solutions, Inc., says the move to state-of-the-art 28nm/20nm planar CMOS and 16nm FinFET technologies present greater challenges to yield than any previous generation. This is putting more emphasis on high sigma yield.

Jamie Girard, senior director, North America Public Policy, SEMI President Obama touched on many different policy areas during his State of the Union talk, and specifically mentioned a number of issues that are of top concern in the industry and with SEMI member companies. Among these are funding for federal R&D, including public-private partnerships, trade, high-skilled immigration reform, and solar energy.

Phil Garrou finishes his look at the IEEE 3DIC meeting, with an analysis of presentations from Tohoku University, Fujitsu’s wafer-on-wafer (WOW), ASE/Chiao Tung University and RTI. In another blog, Phil continues his review of the Georgia Tech Interposer conference, highlighting presentations from Corning, Schott Glass, Asahi Glass, Shinko, Altera, Zeon and Ushio.

Pete Singer recommends taking the new survey by the National Center for Manufacturing Sciences (NCMS) but you may first want to give some thought as to what is and what isn’t “nanotechnology.”

Blog Review November 5 2013

Tuesday, November 5th, 2013

New blogs delve into the packaging technology of Apple’s A7, the road ahead for bulk FinFETs as defined by imec, with EUV is a gating factor for 450mm, split-manufacturing for U.S. trusted IC (TIC) program and Japan’s growing market for equipment and materials.

For the 10nm node and beyond, transistor research efforts are focused on high mobility designs with Ge and III-V channel, reducing VDD supply voltage as well as the subthreshold slope in transistors and optimizing multi-Vt designs. Pete Singer reports on work underway at imec in Belgium.

At the IEEE 3DIC in San Francisco Dan Radack of the Institute of Defense Analysis gave an update on the IARPA trusted Integrated Chip Program. Phil Garrou reports how it is now focused on split-manufacturing with FEOL done off-shore and BEOL done by trusted facilities in the U.S.

The A7 is manufactured by Samsung on a high-κ metal gate (HKMG) 28 nm process and the chip includes over 1 billion transistors on a die 102 mm2 in size. Phil Garrou reports on observations on the Package-on-Package (PoP) design as noted by fellow blogger Dick James. In an earlier blog, Dick described how the Apple A7 is using Samsung’s 28nm process.

Simon Favre of Mentor Graphics notes how EUV could possibly be a gating factor for 450mm. “Would you put in 450mm immersion steppers, and then yank them out to put in EUV before they’re fully depreciated?” he asks.

In advance of Semicon Japan, to be hold December 4-6 at the Makuhari Messe, SEMI’s Dan Tracy and Yoichiro Ando report that restructuring and consolidation has led to a new focus for the semiconductor manufacturers in Japan. As a result, the semiconductor equipment market in Japan will experience double-digit growth in both 2013 and 2014, driven by higher spending for memory production and in spending increases planned for the manufacturing of power semiconductors and “More than Moore” semiconductor technologies. Total equipment spending in Japan is estimated to reach $4.6 billion by 2014. Combining this with the $8 billion-plus spending on semiconductor materials, Japan represents a $12 billion market in 2014 for the suppliers of equipment and materials.

Blog Review October 21 2013

Monday, October 21st, 2013

The readiness of EUV lithography is later than hoped, but appears to be on time for insertion into the 10nm node, which is slated to go into production in late 2015/early 2016. “I’m very convinced that very soon EUV will be ready to enter manufacturing,” said Luc Van den hove, president and CEO of imec, as reported by Pete Singer.

In an earlier blog, Veeco’s Tim Pratt, Senior Director, Marketing, said that indeed the next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. He said that the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV.

Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” said An Steegen, senior vice president of process technology at imec.

EUV readiness also been the focus of several blogs by Vivek Bakshi. Earlier this year, he predicted that 50 W sources will be ready and working in NXE3300B sometime in 2014, corresponding to 43 WPH throughput. 100 W sources will be ready in 2015 or 2016 corresponding to 73 WPH. “The readiness of 250 W EUV sources cannot be safely predicted, unless we see 100 W sources ready and have identified the issues to ensure that they are no showstoppers. I am not convinced that present approaches can get to 500 W sources. It is easy to put them on roadmaps, but delivering them is another question,” he said.

Intel is far ahead of anyone else when it comes to putting 14nm devices into production. However, even Intel finds it challenging. Speaking on a quarterly call with analysts, newly elected CEO Brian Krzanich said 14nm rollout was “about a quarter behind our projections.” He said defects were the problem. “As a result, we are now planning to begin production in the first quarter of next year,” as Pete Singer reported.

Intel already has 3D finFETs in production, and  FinFETs will likely become the logic technology of choice for the upcoming generations, with high mobility channels coming into play for the 7 and 5nm generation (2017 and 2019).

Brian Krzanich also said that Intel remained committed to the transition to 450mm wafers, saying: “We have not changed our timing. We are still targeting the second, latter half of this decade.” At Semicon Europa week, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.

Phil Garrou reports on developments from Semicon Taiwan 2013 of interest to the IC packaging community. The Market Trends Forum chaired by Dr. Burn Lin of TSMC, included a report on DRAM Status (continued consolidation) by Charlie Chan of Morgan Stanley; Nicolas Gaudois Managing Director of UBS Investment Research looked at the “The End of the High End Smartphones Run,” and Dan Tracy of SEMI provided the Packaging Materials Outlook.

Key Trends at Semicon West 2013

Saturday, July 27th, 2013

By Pete Singer

At Semicon West last week (and at The ConFab a few weeks ago) some key trends were clearly evident in the semiconductor industry.

It’s apparent that the world’s appetite for electronics has never been greater. That has increasingly taken the form of mobile electronics, including smartphones, tablets and tablets and the new “phablets.” People want to watch movies and live sports on their phones. They want their mobile devices to be “situationally aware” and even capable of monitoring their health through sensors. That drives higher bandwidth (6G is on the drawing board), faster data rates and a demand for reduced power consumption to conserve battery life. At the same time, “big data” and the internet of things (IoT) are here, which drives the demand for server networks and high performance semiconductors, as well as integrated sensors and inventive gadgets such as flexible displays and human biosensor networks.

It’s also pushing the semiconductor manufacturing industry in new directions. Chip makers typically face tradeoffs between power, performance, area and cost/complexity (PPAC). For mobile devices, the push is to low power, high performance, small area and low cost.

For me, one of the main themes of Semicon West was the demand for mobile devices and how they might impact what has become standard thinking in the semiconductor industry in terms of scaling, performance, power and cost.

At Semicon West 2013, Karen Savala, president of SEMI Americas, kicked things off, noting that it was the 43rd year of Semicon West (32nd consecutive one for me personally). “While much has changed over the years, the one that has been constant is the power of our industry to continually drive innovation, to overcome technical challenges and economic challenges, and develop new processes, new materials and technologies that continue to move Moore’s Law forward,” Savala said. “2013 is no different. The industry finds itself at a critical juncture where multiple technology developments, including 450mm, FinFETs, 3D ICs, advanced materials and processes, and EUV just to name a few, promise to move Moore’s Law ahead. But as we have done before, we will address these challenges, bring new technologies to market, and continue to amaze the world with the power of our collective innovation.”

Karen then introducde the keynote, Ajit Monacha, CEO of Global Foundries, who expanded on his Foundry 2.0 concept, and talked about how the requirements of mobile devices were, in fact, changing the entire semiconductor industry. He noted that the mobile business is forecast to be double the size of the PC market in 2016. The mobile business drives many new requirements, said Manocha, including power, performance and features, higher data rates, high resolution multicore processors and thinner form factors.

This incredible growth is driving new dynamics, said Manocha, and pushing the industry to the new technology node each year, which is presenting the industry with what Manocha deems the Big Five Challenges. Manocha believes these challenges are: cost, device architectures, lithography and EUV, packaging and the 450mm wafer transition. I don’t recall when cost wasn’t an issue, but an audience poll revealed that most people believe economic challenges will be the main factor limiting industry growth, not technical challenges, so cost moves to the top of the list.

After his talk, Ajit was presented with the “SEMI Outstanding EHS Achievement Award — Inspired by Akira Inoue” by Denny McGuirk, president and CEO of SEMI. During Semicon West, SEMI also honored 14 industry leaders for their outstanding accomplishments in developing standards for the microelectronics and related industries

Part of “the buzz” at the show was the rosy prediction issued by SEMI about growth in capital equipment for next year. SEMI forecasts semiconductor equipment sales will reach $43.98 billion in 2014, a 21 percent increase over estimated 2013 equipment spending, according to the mid-year edition of the SEMI Capital Equipment Forecast, released during the show.

450mm in 2017: It’s Coming

Monday, May 27th, 2013

By Pete Singer

The switch to 450mm will likely be the largest, most expensive retooling the semiconductor industry has ever experienced. 450mm fabs, which will give an unbeatable competitive advantage to the largest semiconductor manufacturers, are likely to cost $10 billion and come on-line in 2017, with production ramp in 2018.
Unprecedented technical challenges still need to be overcome, but work is well underway at an R&D center in upstate New York, at the Global 450mm Consortium, G450C. Paul Farrar Jr., the G450C General Manager, recently spoke on the current status of activities, key milestones and schedules during a webcast produced by Solid State Technology.
“At this point, we have contracts with 12 major suppliers, and we have tools that are being delivered to the consortium starting in April and continuing through 2015,” Farrar said.
The G450C team now has over 60 engineers and assignees from the member companies. The goal is to have more than 150 engineers by 2014, with approximately 60 supplier engineers on site. “2013 and early 2014 will be about getting tools installed and up and running. Then the integration and unit process scientists will continue from there,” Farrar said.
Farrar said G450C has commitments for 112 process levels. For 45 processes, two suppliers are developing products (which equates to 90 process levels). A few have three suppliers, and about 10 process steps have one supplier. Farrar said that he sees 300mm and 450mm development continuing simultaneously. “We certainly know that for the next six or seven years, the industry will be developing and bringing capability to both 300mm and 450mm. A key goal here is to make sure that we do not slow down the scaling required for Moore’s Law to go from say 20nm to 15 to 12 to 10, etc. versus the cost reduction you get from going to a larger wafer size. We need to both of these things simultaneously as an industry,” he said. “A rough target is to get to 10nm, and then in 2016 we want to be ready for IC makers to make their decisions on when they will ramp to 450mm.”

450mm Progressing

Sunday, January 27th, 2013

By Pete Singer

One of the highlights of SEMI’s Industry Strategy Symposium held in January in Half Moon Bay, California was the first public presentation of a fully patterned 450mm silicon wafer.
Intel’s Robert E. Bruck, corporate vice president and general manager of Technology Manufacturing Engineering asked Mario Abravanel, Intel 450mm Equipment Program Manager, to join him on stage. Abravanel appeared from behind the stage, carrying the wafer with gloved hands. “It’s real,” Bruck said, noting that the wafer was patterned with 26nm features using nano imprint lithography. Bruck singled out wafer-supplier SUMCO, Dai Nippon Printing for partnering in the mask area, and Molecular Imprints for imprint technology. “It shows that a true partnership can move this thing forward,” he said. Bruck said that Intel will be producing thousands of 450mm wafers in the next few quarters for their equipment partners to use in their own equipment development.
Bruck, during his presentation, noted that fewer companies are capable of delivering Moore’s Law — and fewer capable of 450mm production. He showed that about 20 semiconductor companies have the $3-5 billion revenue “threshold” (measured in 2011 dollars) to build a 200mm fab. Only nine have revenue, in the $9-12 billion range, which is the threshold for a 300mm fab (those being Intel, Samsung, TSMC, Toshiba, TI, Renesas, ST Micro, Qualcomm and Hynix). “In 300mm configurations, there’s a much smaller group that can afford a reasonable capital cost as a percentage of revenue,” Bruck said. “If you extend this 300mm model out a few more years, anticipating the next few nodes that come, the list of participants who can afford to build these factories gets even smaller. Somewhere beyond 2015 will be a 450 number which suggests even further concentration.”
The exact timing of 450mm production was explored at ISS in a panel session hosted by Alix Partners. Chris Danely, Managing Director, Semiconductor Equity Research, JP Morgan, said: “From the Wall Street perspective, the triumvirate of Intel, Samsung and TSMC is telling us 2017. 2018 is when it starts to ramp.”

A New Era for Equipment Suppliers

Saturday, September 1st, 2012

By Pete Singer

The semiconductor equipment industry received quite a jolt recently. In July, lithography equipment supplier ASML announced a customer co-investment program that enabled minority equity investments in ASML (up to 25% total) by its largest customers. Customers could also make commitments to fund ASML’s research and development (R&D) spending for future programs.

Intel was the first investor, acquiring 15% equity ownership interest in ASML. R&D funding and equity investment agreements totaled approximately $4.1 billion. Part of the deal was a contractual commitment from Intel for advance purchase orders for 450 mm and EUV development and production tools from ASML. ASML has said the results of the technology investments will be available to every semiconductor manufacturer with no restrictions.

In August, TSMC joined in, taking a 5% stake in ASML, worth about $1.04 billion. TSMC also committed about $341 million, spread over 5 years, to ASML’s R&D programs.

The Intel announcement made instant believers out of many that both EUV and 450mm would actually happen. Both technologies have been significantly delayed beyond initial target dates, and the thinking was that some massive investment would be required to get them production-ready in a reasonable timeframe (i.e,. 2015-2020). $5+ billion is a pretty good start!

Not only does it seem to ensure that EUV will succeed, but it removed one of the most significant barriers to 450mm development. Even if 450mm solutions were developed for all the other types of process equipment — deposition, etch, ion implant, CMP, cleaning, etc. — it would be going nowhere without EUV. Now, seemingly overnight, 450mm seems inevitable.

It is a new era for semiconductor manufacturing equipment suppliers, for they must now seriously tackle the 450mm challenge, but don’t expect a blossoming new model based on customer co-investments anytime soon. There are at least two competitors in other markets, and developments will likely be funded the way they always have been — though good old-fashioned capitalism.