GlobalFoundries, IBM, and Samsung Electronics will describe their technology offerings at the 2012 Common Platform Technology Forum, set for March 14 at the Santa Clara Convention Center.

Technologists from the three companies, which offer fab-compatible foundry services, will discuss their 28-, 20- and 14-nm processes, as well as innovations beyond 14nm. The event will include discussions of 450mm wafer manufacturing as well.

The forum’s Partner Pavilion, including EDA, IP, library, mask, packaging, and design services companies, will focus on the ecosystem of design enablement and implementation.

Registration is now open for the complimentary, one-day event at the Santa Clara Convention Center.

By David Lammers

MEMS are going through the roof. Optoelectronics, sensors, and discretes (OSD) are growing nicely. But economic uncertainty is putting a serious damper on capital investments for the semiconductor industry and business in general, speakers said at the SEMI Austin Industry Outlook Forum, held Wednesday (Nov. 2^nd).

Bill McClean

“Uncertainty is the worst. People don’t know how to handle it well,” said Bill McClean, president of IC Insights Inc. (Phoenix), predicting a 16 percent decline in semiconductor-related capex for next year.

“If corporations and consumers know that things will be bad, they can adjust,” he told the SEMI Austin audience. But the current iffy environment results in a “corporate freeze, where managers don’t know what to do. If they invest and things don’t go well, it looks like they made a bad decision,” McClean said, adding that “companies have tons of cash, but they are sitting on it and waiting.”

Economist Jon Hockenyos made a similar point about uncertainty, saying that he sits on the board of a mid-sized bank which currently is making almost no loans unless the applicants can offer real estate as collateral. Trying to value potential lenders’ collateral in today’s uncertain environment is so full of unknowns that the bank has essentially stopped lending. “It is unfortunate, but that’s the way it is,” Hockenyos said, estimating that corporations have a $2 trillion mountain of idle cash now.

“Uncertainty means that production capital is sitting on the sidelines,” said Hockenyos, adding that “people’s sense of prosperity is not good right now, and that is probably not going to change next year.”

Capex to Decline 16 Percent

IC Insights predicts that the semiconductor industry will grow about 2 percent this year, with about half of the revenue growth coming from strong sales of the OSD category, set to grow 10 percent this year and continue on a similarly strong pace next year.

Capital expenditures were $16.3 billion in the first quarter, $16.8 billion in the second quarter, and are forecasted to be $15.3 billion in the third quarter and $13.3 billion in the current fourth quarter. “We are heading downward,” McClean said, predicting that semiconductor capex will be in the $12 billion-per-quarter range next year. “It will stabilize, but we see capex down 16 percent year-on-year,” he said.

There are bright spots. “We just raised our smart phone forecast again,” McClean said, noting that Chinese consumers will buy 310 million cellphones, 19 million cars, and 46 million TVs this year. “China is not just about low-cost manufacturing. It is about the Chinese being the world’s leading consumers in many of these electronics system areas.” And over the next decade, India’s GDP growth rate may exceed China’s, potentially giving the world economy a two-fisted growth engine.

The U.S. economic growth rate is depressed by high unemployment, which stems partly from the weak housing market. U.S. homebuilders will build about 700,000 fewer homes than normal this year. With each home accounting for an average of four jobs, the housing market is a major contributor to high U.S. unemployment, McClean said.

Marcus Lentz, who manages the Sematech/ISMI Industry Economic Model, said the semiconductor industry’s fab utilization rate stood at 88 percent in August 2011, almost exactly the industry’s ten-year (2001-2011) average utilization rate of 87.5 percent.

“In the first half of 2011 the industry was increasing capacity, but since mid-year demand has been falling, causing utilization to drop. People are concerned that it could be headed to the low 80 percent range,” Lentz said, adding that at that point companies probably are not making an operating profit.

Moreover, capital efficiency is weakening. The semiconductor industry has thrived largely because a dollar of invested capital has resulted in many more transistors produced at much lower costs. However, Lentz said that beneficent capital efficiency curve started flattening in 2009. “If we see a flattening out of productivity over the next three or four years, that essentially impacts Moore’s Law. Something needs to be done, which is why companies are thinking that if 450mm wafers come on line they can get some of that productivity back,” Lentz said.

Jan Vardaman

Jan Vardaman, president of packaging consultancy TechSearch International, said packaging provides a way to boost performance and density, provided that circuit designers and packaging engineers collaborate on a product’s definition. However, the roadmap for 3D TSVs keeps getting pushed out, partially because bonding, thin-wafer handling, and probe/test are taking more time than expected.

“The industry is making a lot of progress on TSV yields. But we need reliability data, and I’ve seen zero data so far. We need to see drop tests on these phones,” Vardaman said.

Xilinx ships 2.5D FPGA (Source: Xilinx)

There is here-today excitement about interposers, based partly on the success of Xilinx’s Virtex 7 LX 2000T product. “Xilinx is moving the industry into the era of 2.5D silicon interposers. Right now TSMC wants to do all of it so they can guarantee good yields, but some people are not comfortable about having all of it done at one place,” she said, arguing that the OSATs (out-sourced assembly and test providers) need to play a bigger role going forward.

By David Lammers

The late September news of the G450C collaborative effort swept over the Atlantic like a tsunami, starting in Albany, N.Y., and washing up on the Semicon Europa conference, where speakers questioned how European suppliers would be linked in to the Albany-based effort. With a vibrant equipment and materials industry, Europe seeks to play an active role in a transition being managed far from its shores. The issue is complicated by the lack of a single Europe-based IC vendor ready to embrace the larger wafers.

The Global 450 Consortium based in Albany, N.Y. (G450C) plans to have 50 tool types installed at its pilot line in the next few years, said Tom Jefferson, in charge of the ISMI 450 program which is being rolled into the G450C consortium. The G450C pilot line will swing into action in the second half of 2013 and 2014, with demonstrations targeted at “the 1X node.”

(Source: ISMI presentation at 2011 Semicon Europa)

At Semicon Europa, held in mid-October in Dresden, Germany, Jefferson said G450C  will provide “centrally aligned requirements” to suppliers, including a “well-defined method of testing tools and data sharing with the device makers which avoids duplication of data generation.”  (The following week, during ISMI Manufacturing Week in Austin, Texas, the 450mm equipment testing parameters were described at an all-day seminar.) The initial patterning will be performed by an EV Group 770 nanoimprint tool, now being modified at the EVG engineering center in Austria to handle the larger wafers.

Tom Jefferson

While stopping short of saying suppliers would be shut out from purchase orders if they fail to participate in the G450C effort, he said those vendors would receive “a lower priority.” With Jefferson holding out several carrots to the equipment and materials providers to participate, the equipment makers are still looking for assurances on timing as well as financial support.

Asked whether EUV would be a gating factor for 450mm development, Kirk Hasserjian, vice president of strategic programs at Applied Materials, said a successful transition to 450mm “has more to do with the sharing of risk” than whether 450-capable EUV tools are available. “The seeds are in place in New York for better collaboration. Hopefully, there will be some sort of cost sharing and risk sharing going forward.”

He said wafer fab equipment sales are “whiplashed by GDP fluctuations,” and called for “a synchronized transition to 450mm in terms of high-volume manufacturing,” and “a clear, published strategy by the litho suppliers.”

The 450mm progress review sessions at Semicon Europa, organized by Lothar Pfitzner of the Fraunhofer IISB, included 21 presentations over two full days. Jefferson kicked things off by telling the largely European audience that G450C welcomes participation by the European equipment and materials (E&M) industry, which accounts for a surprising 20-25 percent of the worldwide market (led by ASML). “I want to encourage equipment suppliers to participate,” Jefferson told the Semicon Europa audience, adding that they would have access to patterned and unpatterned wafers, shared metrology tools, shipping containers called MACs, and access to the engineers assigned to the G450C by the five device makers – IBM, Intel, GlobalFoundries, Samsung, and TSMC. For European equipment makers not able to ship a tool to Albany, Jefferson said that “participation does not necessarily mean that a tool must be on-site. We need to work out the details” on remote links.

Georg Kelm

Georg Kelm, head of the nanoelectronics sector at the European Commission, summed up the bifurcated European attitude to the 450mm transition: “The (European) materials suppliers are ready to join. The equipment suppliers are equally active, with a proactive attitude. But the IC manufacturers have made no commitments – not yet.”

While much of the EU’s research has gone towards the “More Than Moore” sectors of MEMS, LEDs, photonics, and related subjects, Kelm warned that a successful More Than Moore strategy depends on leading-edge fabs being started for “More Moore” device scaling.

“It would be a mistake to separate More Than Moore and More Moore,” Kelm said, adding that More Than Moore “will not provide a long holiday” for the European semiconductor industry. Much of the effort to link devices with 3D interconnects will end up being done on 450mm wafers, for example.

Kelm said that tool vendors at some point will stop developing new technologies on 300mm platforms. “The 8nm node likely will be for 450mm equipment the equivalent of 65nm for the 300mm equipment. That is when new technologies were 300mm only,” he said. And he predicted that all “post CMOS” manufacturing will be on 450mm tools.

“In 15 to 20 years even the mature technologies will be on 450mm,” Kelm said, adding that “it is possible that some product categories may never be produced in 450mm; however, provided volumes are there, even MEMS, specialized technologies and power could be made on 450mm wafers.”

However, public funding from the European Union cannot be divided long between 300mm and 450mm platforms – there is not sufficient money for that. And he noted that the European equipment and materials vendors – eager to remain competitive with 450mm offerings – employ more people in Europe than the European device makers, including STMicroelectronics, Infineon, and NXP Semiconductors.

“One of the three indigenous IC vendors definitely has to go to 450. The other possibility is that one of the inward investors – Intel or GlobalFoundries — will go to 450 millimeters,” Kelm said.

Hans Lebon, Imec’s vice president in charge of fab and process step development, said “all innovation will move to 450mm, though not in the next two nodes. Ten nanometer technology and beyond will largely be developed on 450, and 300mm will no longer be cost effective.”

Imec will develop the main 450mm process modules at an expanded cleanroom in Leuven, Belgium. Epitaxial deposition, atomic layer deposition, front-end-of-the line critical cleaning, lithography, and dry etching steps all will be developed on 450mm equipment at Imec, Lebon said. “We have a tremendous amount of work to do in a reasonable time frame to keep costs under control,” he told the Semicon Europa audience.

Michel Brillouet, senior advisor at CEA-Leti, predicted that by the 8nm node that some logic vendors will adopt a heterogeneous CMOS technology, in which a III-V material is used in the NFET channel and perhaps germanium in the PFET channel. By the 8nm node the MPU makers, for example, will not be using the same toolset employed today, he said.

Predicting that 450mm would reach volumes in 2018, Brillouet said it is likely that the semiconductor industry will be spread out over various technology generations then. One possible scenario, he said, is that MPU makers would be at the 8nm generation, foundries at 14nm, flash at 11nm and DRAM at 16nm. Leti will continue to work closely with Soitec, Mapper, and other vendors, cooperating closely with Imec on 450mm modules not available at the Leti research facilities in Grenoble.

Heinz Kundert, president of SEMI Europe, said about 40 European suppliers have participated in the EU-based EEMI 450 Initiative. A March 2011 SEMI Europe survey showed that half of the equipment and materials respondents said 450mm was “very important to my company.”

By David Lammers and Mark LaPedus

In a major shift, the Sematech ISMI 450 program will become part of the Global 450 Consortium announced yesterday by New York governor Andrew Cuomo, Sematech officials said Wednesday (Sept. 29).

(Source: Sematech ISMI 450 program presentation)

Since 2006, the Sematech ISMI organization has been in charge of the early stages of the 450mm transition, including developing standards for the wafers, automation, and getting the ball rolling for development of the 450mm processing tools. Last year, the entire ISMI organization moved to Albany, N.Y., from Austin, Texas, and the state of New York invested an estimated $300 million in the 450mm program at ISMI. Intel assignee Tom Jefferson headed up the ISMI 450 program, with another Intel assignee, Tom Abell, serving as the point man for many of the negotiations with the tool suppliers.

In a parallel track, Intel, Samsung and TSMC – the so-called IST group of device makers supporting the 450mm transition – began plotting a timeline for 450mm-capable pilot and production lines.

The announcement of the Global 450 Consortium consolidates the 450 effort into one consortium, with access to the new CNSE Fab West building now under construction at the CNSE campus.

Fab construction firm M+W is building a $300 million research center at the University at Albany’s College of Nanoscale Science and Engineering (CNSE) at the University at Albany, which will be part of the Global 450 Consortium, according to a spokesman for the CNSE.

The building will be ready to install the fab equipment by July 2012, according a report from The Business Review, an Albany-based  news Web site, citing Alain Kaloyeros, senior vice president and CEO of the Albany Nanotech complex, as its source. The new building, according to the report,  will include a 50,000 square ft. cleanroom and have room for 800 employees.

A Sematech spokeswoman sent out a statement, which indicated the Sematech ISMI 450 program “has built the foundation for where the industry is today in the transition to 450mm, and our program is now a part of the new initiative, which will build on and expand our efforts.”

Bob Johnson, a Gartner analyst, said the transition from a Sematech-led 450 program to a separate consortium using the CNSE facility makes good sense. The overall 450 program is moving into a more expensive phase, where beta tools must be developed and tested, and a comprehensive process flow must be proved out. That will take many billions of dollars, and duplicating efforts is not an option.

“This is an example of where the four big companies – Intel, GlobalFoundries, TSMC, and Samsung – decided to step up to the plate and get this going in ways the 450 program couldn’t do,” Johnson said, adding that Toshiba remains the only large chip manufacturer outside of the new consortium. Micron Technology and Elpida also are mulling their 450 options, he noted.

The CNSE Nanotech operation has proven its ability thus far to protect IP, even where competing firms are operating side-by-side, he noted.

Gartner’s team of analysts has created a timeline which foresees a 450mm volume fab going into operation in 2018-2019. The major equipment companies, such as Applied Materials and Novellus Systems, may have beta tools ready next year, Johnson said. The new Global 450 Consortium may support some of the beta tool development efforts, he added.

The pilot line at Albany Nanotech will move into operation in 2013, with the participating companies working out the bugs from the process. The major device makers will set up their own pilot lines around 2016-2017, he said.

“The companies have to make sure that their processes yield chips at the same rate on 450 wafers as they do on 300 millimeter wafers,” he said.

One important question is how the lithography tool vendors will handle the 450 transition. Any 450 line will need both EUV and 193nm tools. And the throughputs must improve so that the device makers will see the cost savings which drive the move to the larger wafer size.

The Global 450 Consortium is “an efficient way to do the R of the 450 R and D. It is a way to go from concept to a feasible set of tools and processes,” he said.

By David Lammers

Semiconductor equipment executives participating in the Citi Technology Conference in New York earlier this week said development work on 450mm-capable equipment is picking up, but uncertainty continues over the timing of the transition.

Rick Hill, the CEO at Novellus Systems Inc., said he expects suppliers and semiconductor vendors to meet during the SEMI International Trade Partners Conference, set for Nov. 6-9 in Hawaii, to discuss funding mechanisms for 450mm R&D.

Intel, Samsung, and TSMC have said they would like to begin using the larger wafers in the middle of this decade, at the 14nm node or later.

Hill expressed skepticism about a fast transition to the larger wafer size. “First we have to have EUV before any transition to 450mm can occur. We can’t have an EUV tool with a throughput of six wafers per hour like we have now and expect it to be economically viable,” Hill said.

The Novellus CEO said he expects only three companies to make an early transition to 450mm. Since many companies will never build 450mm fabs, it will cause a divide among Novellus’s customer base, Hill said.

“Right now we are looking at the technology roadblocks,” he said, listing heavier wafers, uniform plasma densities, and electroplating as challenges. “For ECD, maintaining a uniform current, so we can plate at exactly the same thickness – putting down that 1000 Angstrom seed layer – promises to be a very difficult challenge,” he said.

George Davis, the chief financial officer at Applied Materials, said Applied “will ship some 450mm tools next year.” Applied will shift from relatively inexpensive design-related work going on now to 450mm tool building in the first half of 2012.

“We will start bending metal in 2012,” Davis said.

He reiterated a statement made during Semicon West, that Applied will invest slightly more than $100 million next year in 450mm equipment development.

Asked when the transition to the larger wafer diameter will begin, Davis said “it is very hard to call a consensus on when customers want 450mm equipment,” but added that Applied “wants to support our customers’ roadmaps.”

Asked if Applied sees the 450mm wafer transition as an opportunity to gain market share, Davis said the wafer transition is “a big enough inflection point that it does represent a share gain opportunity.”

Ernie Maddock, the chief financial officer at Lam Research, told the Citi conference participants that “there are opportunities for Lam Research at 450. Any time there is a major inflection point, we want to be very well positioned.”

(Source: IC Knowledge)

“We want to move with them,” Maddock said, referring to the companies committed to 450mm pilot lines. “It is a difficult challenge figuring out the timing. Some are saying they want it pulled in, others that they expect it to be pushed out. We want to go through a thoughtful process and think about the industry’s investment portfolio.”

All of the executives said their companies are spending more on R&D. Maddock said Lam is working with its customers on five major technology areas: through-silicon vias (TSVs), vertical NAND structures, 3D DRAM structures, 3D logic transistors, and the transition to 450mm wafers.

To some extent, investments in 450mm fabs depend on chip demand and the economic health of the semiconductor industry. Hill said Novellus believes overall demand for semiconductors is “fairly good.”

“Our customers are up one day, down the next. Nine months from now things might be different, but right now most don’t feel very good about things, so they tend to wait. It is not like 2009, when the industry was in a cash crisis. We are in a period of lack of confidence, not lack of demand,” Hill said.

Davis said the industry is in “one of those periods where there is a lot of volatility.” While some customers are putting orders on hold, few are cancelling, and many customers are hoping for a strong Christmas shopping season to spur demand for integrated circuits.

By David Lammers

A Semicon West panel on the 450-mm wafer transition was far more positive than previous sessions over the past five years. However, equipment executives said they remain concerned that the timing of the transition and the targeted technology node will change, and change again, before 450-mm equipment starts shipping in volumes.

David Hemler, vice president of new product development at Lam Research, said he believes demand for equipment will continue to rise, with more pieces of equipment sold even as the 450-mm wafer generation takes hold. “That part of the economics I think is OK. The problem comes if there is a false start. If the device makers first say they want it for 14nm, then change to 7nm, that is double the investment. If we could know that 450 would come in at this date, at this node, we could do that. That risk of the unknown is the trouble,” Hemler said.

Hemler later added that such certainty is highly unlikely. “Even within TSMC, Samsung, and Intel, different people are talking about different scenarios.”

“We cannot afford a false start,” a participant said. “We have to make certain we know the design node – that is critical.”

Paola Gargini (Intel), Tom Sonderman (GlobalFoundries) and Bob Johnson (Gartner).

Intel technology strategy manager Paolo Gargini said equipment makers should “overshoot” as they develop the technology capabilities of their 450-mm tools, protecting themselves from possible delays. He said Wall Street now expects the 450-mm transition to occur in the 2016-2019 time frame, but added that trying to pin down the both the node and exact year of entry is asking for the impossible.

Gargini also said the need for leading-edge equipment for 300-mm wafer processing will continue “forever.” He said the idea that all the most capable equipment will move to 450-mm from 300-mm is false, and is “causing alarm bells to go off” by people working at mid-size companies in the IC industry.

“There has to be a method where the equipment makers can scale up the tools that they ship, with two tools (300-mm and 450-mm) with essentially the same capability. There has got to be coexistence,” Gargini said.

The three semiconductor companies backing the 450-mm transition – Intel, Samsung, and TSMC – held a meeting last year and identified some 60 tools that they all use in common. The remaining one-third of the most important tools differ from company to company, but by together asking for 450-mm models of the 60 tools used commonly the transition could be accelerated, Gargini said.

Tom Sonderman, vice president of manufacturing technology at GlobalFoundries, said companies are set to invest in EUV scanners, with GlobalFoundries planning to take possession of an ASML NXE:3300 EUV scanner next year. “The gating factor for 450-mm is lithography,” Sonderman said, prompting Gartner analyst Bob Johnson to ask, “When will ASML commit to 450?”

While EUV is an important piece of the 450-mm toolset, scanners expose in a die-to-die manner, regardless of the wafer size. Shifting to 450-mm scanners would require a different wafer stage, of course, but one source said ASML has designed its chambers to be extendable to the 450-mm wafer size. “Lithography won’t be the problem,” he argued.

Sonderman said “we need synchronized planning” to make the 450-mm transition successful.

“There clearly lots of things we can do to get more out of our 300-mm investments, while we are on the way to 450. Let’s not leave any productivity gains on the table. When you look at how much silicon sits in the fab, and how much we throw away, there is a lot we can do,” Sonderman said.

When 450-mm fabs are built, there almost certainly will be major changes to automation systems. “The number of wafers we move around certainly will not be 25 to a FOUP. They way we layout a factory, and the way we automate a factory, will change,” Sonderman said.

Novellus subsidiary Peter Wolters GmbH (Rendsburg, Germany) said it has introduced new gap measurement technology for double-side silicon prime wafer polishing (DSP), employing high-resolution sensors and new software algorithms. The advances in the AC2000-P³ system result in improved wafer quality control and higher throughputs, the company said.

In order to achieve ultra-flat wafer geometries, double-side polishing is the technology of choice to manufacture 300 mm and 450 mm prime silicon wafers.  The polishing wheel gap dimension and control throughout the polishing process is critical in determining the total within-wafer and wafer-to-wafer thickness variation (GBIR/TTV), the company said.  Figure 1 shows the impact of gap profile control on the GBIR measurement, a measure of the final prime wafer quality.

Source: Peter Wolters

To address the need for precise polishing wheel control during the double-side polishing process, Peter Wolters engineers incorporated several innovative features into the latest variant of the AC2000-P³ system.  New contactless gauges with increased accuracy now provide sub-micron resolution during the in-situ gap measurement.  This new sensor technology has been incorporated into Peter Wolters’ upper platen adaptive control (UPAC) system and provides faster response times to process variations incurred throughout the polishing process.

Additionally, the AC2000-P³ polishing process uses the industry’s first non-contact, sensor-based end point detection feature. This technology ensures repeatable within-batch and batch-to-batch wafer thickness, along with extremely low edge roll-off values (ESFQR).

Source: Peter Wolters GmbH

The new sensor technology incorporates a proprietary software algorithm that replaces time-based statistical process control (SPC) to precisely measure the final wafer thickness.  By eliminating non-value added polishing time, the system throughput has also been significantly increased.

“In preparation for next generation technology nodes, the new gauges and software algorithms developed for the AC2000-P3 will provide our customers with the combination of high productivity, process flexibility and precision polishing control that they require,” said Dave Celli, chief executive officer of Novellus’ Industrial Applications Group. “While designed for today’s 300 mm wafers, the AC2000-P³ can also simultaneously process up to five 450 mm wafers, thus preparing Peter Wolters’ customers for the next wafer size transition as well.”