By Mark LaPedus
The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond.

Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography.

The sea of change likely will add to the burden on the foundries, which are already under stress as they continue to do more of the R&D and heavy lifting for their customers. At present there is debate about what changes will be needed for this extra load, as well as the looming inflection points on the process and transistor fronts. But the future seems clear in one respect—some changes will be needed.

Intel has taken a big lead in the process race and the foundries are struggling to keep up. In addition, the cost-per-transistor curve has been falling at about 29% per node to enable cheaper systems. At 28nm and 20nm, however, the curve is leveling off at the foundries.

“The fabless companies at the leading-edge, such as Nvidia and Qualcomm, are visibly concerned about their foundries’ ability to keep up with Moore’s Law,” said G. Dan Hutcheson, president of VLSI Research. “To stay in the game, they need a steady decline in cost-per-transistor. If (the curve levels off), this certainly puts into question the common wisdom that the fabless-foundry model is impenetrable.”

The pressure resides squarely on the leading-edge foundries, GlobalFoundries, Samsung, TSMC and UMC, to keep up and deliver. Outside of Intel, vendors face a challenging transition from today’s planar technology at 20nm to finFETs and other architectures at 14nm and beyond.

They also must select between various CMOS technologies to enable scaling. Foundries are leaning towards bulk technology for planar at 20nm and finFETs at 14nm. A rival camp has made a case for silicon-on-insulator (SOI) technology. On the transistor front, there is talk about a hybrid finFET/planar approach. SuVolta has a new planar transistor option. And 3D stacked devices provide yet another avenue.

It’s unclear which technologies will emerge as the winners or losers. What is clear is that only companies with deep pockets can afford to participate. At 22nm, a fab runs $6.7 billion, process R&D is $1.3 billion, and design costs are $150 million, according to GlobalFoundries. And it will cost a staggering $32 billion in total process and tool R&D alone to develop 450mm fabs, according to VLSI Research.

Nonetheless, the fabless-foundry model appears to be far from broken, and predictions about the death of foundries seems greatly exaggerated. The pure-play foundry market is projected to reach $29.6 billion in 2012, up 12% from 2011, according to IHS. This business will grow by 14% in 2013, with double-digit growth continuing in 2014 and 2015, they said.

20nm challenges
Still, the 20nm node represents a pivotal juncture. Intel has made the shift from conventional planar transistors at 32nm to 3D finFETs at 22nm. For foundries, 20nm represents the last node in the planar era, because planar is beginning to suffer from undesirable short-channel effects.

And previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process. “As we move to 20nm, the fundamental differentiation between high-performance and low-power processes is going away,” explained Mojy Chian, senior vice president of design enablement at GlobalFoundries.

This move, coupled by delays in past nodes, prompted some industry pundits to imply that the fabless-foundry model is somehow broken. Chian dismissed the notion, saying the “fabless-foundry business is thriving.”

So what will keep the fabless-foundry model viable? There must be more collaboration and a new mindset, in which the foundries must change from being mere manufacturing partners into virtual IDMs, Chian said. “New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the time-to-market,” he said.

Vendors must also make some tough choices. On the CMOS front, for example, the foundries will generally move to conventional bulk silicon at 20nm, due to cost. GlobalFoundries is in the bulk camp, but it will also make select chips for IBM and STMicroelectronics using fully depleted SOI (FD-SOI) at 28nm and 20nm.

Regarding SOI, Soitec is offering another CMOS technology option. It provides SOI for planar (FD-2D) and finFET (FD-3D) devices. FD-2D has 241 process steps, compared to 328 for bulk, according to Soitec. SOI wafers are more expensive, but IC makers can offset the costs with fewer process steps, more performance and less power, said Steve Longoria, senior vice president of strategic business development at Soitec.

Jeff Lewis, senior vice president of marketing and business development at SuVolta, said the industry needs a new solution besides bulk and SOI at 20nm. “The cost-per-transistor is higher at 28nm than 40nm/45nm,” Lewis said. “The problems get worse for the 20nm node due to double patterning.”

Another problem is transistor threshold voltage variation, which is caused by systematic and random variations, he said. A phenomenon called random dopant fluctuation (RDF) causes more than 70% of all random variations at 65nm and the problems are getting worse at each node. “In scaling, you start to get mismatches from one transistor to another,” Lewis said. “So the threshold voltages start to vary.”

To solve RDF and other problems, SuVolta recently rolled out a new transistor option that extends conventional bulk CMOS technology. SuVolta’s Deeply Depleted Channel (DDC) technology works by forming a deeply depleted channel when a voltage is applied to the gate.

Beyond 20nm
The problems continue to mount beyond 20nm. It’s unclear if EUV will be ready for the 14nm node. So, IC makers must contend with costly multi-pattering schemes. On the transistor front, Intel has made the migration to finFETs, but its technology has been a hot topic of discussion. Some “have painted Intel as being in trouble with tri-gate because images from a tear-down showed the fin was not squared off, but more shaped like a half-oval,” VLSI’s Hutcheson said.

Others have shown more vertical fins. “It’s very doubtful that Intel is in trouble,” Hutcheson said. “To get a squared off shape would be easy, but it adds steps, hurts yields, and dramatically increases cost.”

Intel may have made some tradeoffs to solve one bulk finFET challenge: height variation. In finFET production, there is an etch step, followed by a back-fill oxide process, and then an implant for junction isolation. The hard part is to make fins with consistent heights during the etch process.

Because of height variability, there are fears that the foundries could struggle making bulk finFETs with any consistency. In response, one foundry claims to have overcome some of these obstacles. According to a paper at the recent IEDM, GlobalFoundries implemented a dual shallow trench isolation (STI) process to ensure fin height control. Its high-k/metal-gate scheme also helped construct “tall/narrow” fins with less doping for better RDF, according to the paper.

FinFETs provide a 40% improvement in power reduction, but the technology still doesn’t put the cost-per-transistor back on the 29% reduction curve. “You are getting a significant power advantage,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “It’s still a challenge to translate that to a die cost reduction.”

All told, the industry should take a harder look at SOI, said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. “FD-SOI is a fairly simple process, but there is a cost penalty,” Patton said. “When you get to finFETs, it’s a different story. The cost issue becomes neutral between bulk and SOI. Variability is also an advantage for SOI for finFETs.”

In the SOI model, “you place your order to the substrate supplier,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that promotes SOI. “The height of the fin is pre-determined. It’s pre-made for you.”

Fin variability in bulk finFETs is about 140% to 170% higher, versus SOI finFETs, according to the SOI Consortium. In the front-end-of-the-line (FEOL) process alone, SOI finFETs have 56 process steps, compared to 91 for bulk finFETs, the group said. In total, the FEOL cost for SOI finFETs is $561, compared to $805 for bulk, they said.

Still, GlobalFoundries, TSMC and Samsung are banking on bulk finFETs at 14nm for two reasons. First, it’s unclear if the SOI wafer suppliers can meet demand during crunch times, said GlobalFoundries’ Kengeri. “Historically, customers are not used to designing in SOI. They are comfortable designing with bulk,” he said.

What’s next?
Beside traditional finFETs, there is also talk about a hybrid approach. In this concept, chip makers would combine finFETs and planar devices on the same chip. The planar devices could include analog IP. “This is not easy to do,” Kengeri said. “It’s a complicated process.”

A more likely scenario is that current finFET technology would be scaled at least two generations to 10nm, he said. Then, at 7nm or before, the industry is looking at various next-generation finFETs to solve the mobility problems. The candidates include quantum well finFETs, PMOS germanium finFETs, and SOI. “From a research point of view, we’re looking at everything, but nothing is settled,” Kengeri said.

By Mark LaPedus
The initial round of stacked 2.5D and 3D chips based on through-silicon vias (TSVs) has emerged in the market.

There are other 2.5D/3D chips in the pipeline, but it’s taking longer than expected to bring these devices into production. There are a range of design, manufacturing, supply chain and cost challenges associated with 2.5D/3D designs.

The enormous risk to bring these chips to market means that vendors must develop a sound and cost-effective strategy on all fronts. In one part of the wafer-level packaging flow, for example, chipmakers must choose between one of the three main vertical stacking techniques: die-to-die, die-to-wafer and wafer-to-wafer.

Each stacking technique has its advantages and disadvantages. The decision to go with one technique or another depends on the product type, process flow, and, of course, cost. And it also involves some changes in the interconnect material and wafer bonding methodology.

The early stacking trends are becoming apparent: The 2.5D/3D chip market is currently embracing die-to-die (sometimes called chip-to-chip), with die-to-wafer in the works. Wafer-to-wafer has moved into applications such as image sensors, but the technology is still in the distant future for chip production.

“I think the biggest challenge for the whole process is yields,” said David McCann, senior director of technical business operations for packaging and central engineering at GlobalFoundries.

“Die-to-die is the first implementation. In die-to-die, you can manage the warpage and isolate the yield,” McCann said. “Wafer-to-wafer will take place in the future, but you bring yield issues into your business model.”

Another foundry, Taiwan Semiconductor Manufacturing Co. (TSMC), recently rolled out its Chip-on-Wafer-on-Substrate (CoWoS) offering. This is a turnkey line that includes both the front- and back-end steps for 2.5D/3D production. Technically, CoWoS is a die-to-die scheme, but it could also be classified as die-to-interposer.

Bottleneck in 3D flow
In the overall 2.5D/3D manufacturing flow, there are a number of process steps. There are five main front-end TSV or via creation process steps: etch, chemical-vapor deposition, physical-vapor deposition, electroplating, and chemical mechanical polishing.

The bigger manufacturing bottlenecks reside at the back-end. In this flow, a processed wafer with TSVs goes through the following steps: wafer bumping, thinning, stacking and bonding. Test is conducted at the wafer level and during various points in the flow.

Test and the temporary bonding/debonding steps are still the big challenges. Though not as daunting, there are some challenges in the various stacking techniques, including die-to-die.

One of the first 2.5D chips in the market is Xilinx’s Virtex-7 2000T FPGA. The recently announced 2000T is a 28nm part, in which four FPGA slices are stacked on a 65nm interposer. Technically, Xilinx’ FPGA utilizes chip-to-chip and die-to-interposer stacking.

Emerging 3D memory devices utilizing Wide I/O also will implement die-to-die. Related to stacking, the industry is also moving to an emerging interconnect scheme called fine-pitch copper pillar bumps for 2.5D/3D designs.

For years, many 2D designs have used conventional flip-chip solder bumps. More recently, copper pillar bumps have been implemented in various 2D designs, when there is a need for low-profile and high-connectivity applications.

“Copper pillar gives you a tighter pitch,” said Sesh Ramaswami, senior director of strategy for the TSV program at Applied Materials. Flip-chip solder bumps enable 40-u pitches, compared to 20-u for copper pillar, Ramaswami said.

The transition to copper pillar bumping appears to be rather painless, but there are some issues in the vertical stacking flow. Compared to the other stacking techniques, die-to-die is well understood, and the supply chain is relatively straightforward.

The die-to-die equation becomes more difficult in heterogeneous designs, where the individual parts may come from two or more vendors. This complicates the stacking flow and brings yield into the equation. “That’s where the (importance of a good) supply chain comes in,” Ramaswami said.

The other problem with die-to-die is throughput and cost. In die-to-die, the components are assembled and aligned with traditional pick-and-place tools. The throughputs are slow, sometimes averaging 360 dies an hour. “The problem is more pronounced if the dies are small,” said Thorsten Matthias, head of business development at EV Group, a supplier of semiconductor equipment.

Regarding the assembly flow, Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE), added: “It’s really a challenge to handle these thin wafers. Warpage is a big challenge.”

3D devices will require ultra-thin wafers of 100 µm and below, but these substrates are less stable and prone to stress in the flow. This will require a manufacturing step called temporary bonding and debonding, which is still a relatively slow and expensive process.

For this and other reasons, the 2.5D/3D devices themselves are expected to remain expensive. “But for very large die, you can still achieve a cost reduction,” Rice said.

Other stacking options
There are even more challenges in die-to-wafer, which appears to be in R&D or the pilot line stage. Die-to-wafer also has many of the same inherit problems as die-to-die. There are supply chain issues. Both flows will implement expensive temporary bonding/debonding steps.

“The question is how you are going to test it? You really need known-good die (KGD) to put these things together. You also need to make sure your interposer is good,” Rice said.

Still, many chip makers have put die-to-wafer on their roadmaps to lower their costs and boost their throughputs, EV Group’s Matthias said. The other advantage is that “you can control or eliminate warpage,” he said.

Meanwhile, for decades, the industry has been talking about wafer-to-wafer stacking. Wafer-to-wafer enables the highest throughput, but it requires that the dies have the exact same size when bonding. But if a defective die is bonded to a good die, it destroys the whole stack. “Wafer-to-wafer is a long ways off,” said E. Jan Vardaman, president of TechSearch International Inc., a research firm.

To accelerate wafer-to-wafer, the industry is exploring new bonding technologies. Today’s 2.5D/3D devices, based on TSVs and copper pillars, are implementing metal-to-metal thermocompression bonding. This methodology has the advantage of forming the mechanical and electrical bonds in one step.

The industry is also looking at copper-to-copper thermocompression bonding. “Copper-to-copper is a must if you are targeting the highest possible electrical performance at less than 10-u,” EV Group’s Matthias said. But this technology is a slower process and not expected to move into volume production for another two to three years.

Another technology, fusion wafer bonding, could one day enable wafer-to-wafer for 3D chip integration. Fusion bonding is a two-step process consisting of a room temperature bonding step and an annealing step at elevated temperature. EV Group and others sell fusion bonders.

Using one form of fusion bonding technology, dubbed direct oxide bonding, Ziptronix Inc. has demonstrated the ability to reduce distortion in backside illuminated (BSI) image sensors. Ziptronix’ ZiBond process can be performed as wafer-to-wafer or die-to-wafer. The process initiates at room temperature without external force required.

The rival bonding solutions “are limited in terms of stress, cost and scalability,” said Paul Enquist, CTO and vice president of R&D at Ziptronix.

Ziptronix’ technology is in production for BSI image sensors. It’s unclear when chipmakers will adopt fusion bonding for wafer-to-wafer 3D integration. The adoption of new technology takes time. “Our technology has been ready for awhile,” he said. “Finally, the market is ready for the technology.”

By Ed Sperling
Silicon certainly isn’t going away, but most of the innovation in semiconductors won’t involve silicon in the future.

In a keynote speech today at the Industry Strategy Symposium in Half Moon Bay, Calif., IBM fellow Bernie Meyerson said that “we are in the end game” with silicon. “You are getting to the physical limit.”

This has implications for every facet of semiconductor design and manufacturing. The end of classical scaling at 90nm meant that for each new process shrink there would no longer be a guaranteed improvement in performance, power and a subsequent decrease in cost. None of those is guaranteed anymore by shrinking features, and the picture becomes even hazier after 11nm.

Going forward will require massive innovation in gate structures, new lithography technology, different materials and even greater innovation. Gate structures will move from FinFETs at 14nm to other approaches at future nodes. One such innovation IBM is experimenting with is gate-around nanowire. Another is CNTFET, or carbon nanotube FET, where channel lengths have been tested down to 9nm.

“The enormous challenge will be in manufacturing,” said Meyerson. “Silicon is not done, but we’re starting to look at non-silicon devices. There needs to be something else.”

Graphene is one alternative. So far, that has shown promise on a small scale, he said. Other elements in the Periodic Table are also under investigation, either alone or in combination.

Meyerson noted that IBM researchers now have the ability to manipulate single atoms, and have been using that capability to research the minimum number of atoms necessary to retain data in a magnetic memory bit. The number of atoms is 12. Anything less than that results in random data loss due to quantum effects.

The advantage of this approach is that memory chips can be dramatically smaller and density can be increased by as much as 10,000 times over RAM, or 160 times the density of flash, which changes the cost equation far more than a feature shrink.

Stacking die is another approach that can solve some problems, particularly performance limitations, by shortening the signal path between logic and memory. Meyerson said the speed of light is woefully insufficient for improving performance over distance, but shortening the distance in a stack can make up for that. “We’re going to see TSVs in logic sooner rather than later because of the system benefits,” Meyerson said.

One problem with stacked die is heat, however. Meyerson noted that by moving the I/O off the chip that heat can be significantly reduced. About half of the heat produced on a die is from I/O, he said.

In addition, there is value in utilizing research that already has been performed in different combinations. He said the deep integration of that research, other functions and systems requires innovation, as well, which can have effects across the board in IC design and manufacturing.

By David Lammers

Semiconductor equipment executives participating in the Citi Technology Conference in New York earlier this week said development work on 450mm-capable equipment is picking up, but uncertainty continues over the timing of the transition.

Rick Hill, the CEO at Novellus Systems Inc., said he expects suppliers and semiconductor vendors to meet during the SEMI International Trade Partners Conference, set for Nov. 6-9 in Hawaii, to discuss funding mechanisms for 450mm R&D.

Intel, Samsung, and TSMC have said they would like to begin using the larger wafers in the middle of this decade, at the 14nm node or later.

Hill expressed skepticism about a fast transition to the larger wafer size. “First we have to have EUV before any transition to 450mm can occur. We can’t have an EUV tool with a throughput of six wafers per hour like we have now and expect it to be economically viable,” Hill said.

The Novellus CEO said he expects only three companies to make an early transition to 450mm. Since many companies will never build 450mm fabs, it will cause a divide among Novellus’s customer base, Hill said.

“Right now we are looking at the technology roadblocks,” he said, listing heavier wafers, uniform plasma densities, and electroplating as challenges. “For ECD, maintaining a uniform current, so we can plate at exactly the same thickness – putting down that 1000 Angstrom seed layer – promises to be a very difficult challenge,” he said.

George Davis, the chief financial officer at Applied Materials, said Applied “will ship some 450mm tools next year.” Applied will shift from relatively inexpensive design-related work going on now to 450mm tool building in the first half of 2012.

“We will start bending metal in 2012,” Davis said.

He reiterated a statement made during Semicon West, that Applied will invest slightly more than $100 million next year in 450mm equipment development.

Asked when the transition to the larger wafer diameter will begin, Davis said “it is very hard to call a consensus on when customers want 450mm equipment,” but added that Applied “wants to support our customers’ roadmaps.”

Asked if Applied sees the 450mm wafer transition as an opportunity to gain market share, Davis said the wafer transition is “a big enough inflection point that it does represent a share gain opportunity.”

Ernie Maddock, the chief financial officer at Lam Research, told the Citi conference participants that “there are opportunities for Lam Research at 450. Any time there is a major inflection point, we want to be very well positioned.”

(Source: IC Knowledge)

“We want to move with them,” Maddock said, referring to the companies committed to 450mm pilot lines. “It is a difficult challenge figuring out the timing. Some are saying they want it pulled in, others that they expect it to be pushed out. We want to go through a thoughtful process and think about the industry’s investment portfolio.”

All of the executives said their companies are spending more on R&D. Maddock said Lam is working with its customers on five major technology areas: through-silicon vias (TSVs), vertical NAND structures, 3D DRAM structures, 3D logic transistors, and the transition to 450mm wafers.

To some extent, investments in 450mm fabs depend on chip demand and the economic health of the semiconductor industry. Hill said Novellus believes overall demand for semiconductors is “fairly good.”

“Our customers are up one day, down the next. Nine months from now things might be different, but right now most don’t feel very good about things, so they tend to wait. It is not like 2009, when the industry was in a cash crisis. We are in a period of lack of confidence, not lack of demand,” Hill said.

Davis said the industry is in “one of those periods where there is a lot of volatility.” While some customers are putting orders on hold, few are cancelling, and many customers are hoping for a strong Christmas shopping season to spur demand for integrated circuits.

3M and IBM said they plan to jointly develop adhesives for stacking chips vertically into 3D packaging. 3M and IBM said they plan to develop adhesives that can be applied to silicon wafers, coating hundreds or even thousands of chips at a single time as opposed to packaging and bonding techniques that can only be applied to individual chips.

IBM said the joint research will consider the role adhesives could play in conducting heat through a densely packed stack of chips and away from heat-sensitive components such as logic circuits.

“Today’s chips, including those containing ‘3D’ transistors, are in fact 2D chips that are still very flat structures,” said Bernard Meyerson, IBM’s vice president of research. “Our scientists are aiming to develop materials that will allow us to package tremendous amounts of computing power into a new form factor – a silicon ‘skyscraper.’ We believe we can advance the state-of-art in packaging, and create a new class of semiconductors that offer more speed and capabilities while they keep power usage low — key requirements for many manufacturers, especially for makers of tablets and smartphones.”

Under the agreement, IBM will draw on its expertise in creating semiconductor packaging processes, and 3M will provide its expertise in developing and manufacturing adhesive materials.

Herve Gindre, division vice president at 3M Electronics Markets Materials Division said “3M has worked with IBM for many years and this brings our relationship to a new level. We are very excited to be an integral part of the movement to build such revolutionary 3D packaging.”

(Source: IBM)

By Ed Sperling
Competition in semiconductor manufacturing has always been intense at the leading edge, but it’s now also heating up at older process nodes.

While it’s extremely difficult to compete with the likes of GlobalFoundries, Samsung, TSMC and Intel at 28nm and 22/20nm, where the investment in equipment and the manufacturing process can be measured in billions of dollars, the cost to build and fully equip fabs at 65nm and beyond is measured in millions. That significantly changes the ROI equation, particularly when mainstream is still being defined as 55nm and older nodes.

“Over the last few years we’ve seen the volume remain at 65nm,” said Walter Ng, vice president IP ecosystems at GlobalFoundries’ IP, during a panel discussion yesterday at the Global Technology Conference. “But there are a lot of companies doing things that are very relevant today even at 0.25 (microns).”

GlobalFoundries isn’t alone in spotting this trend. “Even though it’s sexy to talk about the leading edge, about 75% of ARM’s royalty comes from cores developed in 2006 and earlier,” said John Heinlein, vice president of marketing for the physical IP division at ARM.

ARM's Heinlein: Mainstream is 55nm and older.

The reasons are almost entirely economic, and they are fostering debate about the continued relevance of Moore’s Law beyond 20nm. That’s not to say the most advanced process nodes are wanting for customers or technology. But there are fewer customers at 28nm and 22nm than there were at 65nm, and the trend points to even fewer chips being designed at future nodes. Moreover, while chipmakers used to move from one process node to the next every two to three years, that is no longer a requirement. Even the most advanced devices have a mix of chips from different process technologies because the volume of chips needed to recoup design and production costs increases at each new process node—and at 14nm it’s hard to imagine many markets that can sustain the necessary volume.

These changes haven’t been lost on a handful of new startup foundries in places like China and Singapore, which see a successful business at older process nodes. In fact, the race for this part of the market has spawned a renewed interest in beefing up some of the technology, particularly when it comes to power and high performance. At 130nm, power was considered an afterthought, for example. But now that these chips are being combined with other semiconductors developed at the leading-edge processes, even they have to be retrofitted to deal with power issues at the architectural stages.

“If you have an existing product, you can look at adding oscillators or an EEPROM developed at an older node to reduce the system cost,” said Jeff Lukanc, director of engineering at IDT. “You have to look at the economics of the lower cost. It’s not always a slam-dunk, but if you look at mixed signal design and RF design, at the leading edge nodes it’s really tough.”

This will become critical in stacked die, where multiple die are thinned out and then stacked together. Power budgets need to be developed for the entire 3D package, not just a single die, so every component needs to be as power-efficient as possible.

“There’s a point at which a heterogeneous multichip package will become attractive,” Lukanc said.

When exactly that happens no one is certain, but foundries and design services companies say they are now creating demonstration chips that will be used in stacked configurations, and memory companies have announced stacked-die packages that are expected to be integrated with logic chips starting in 2012 through an interposer layer or using through-silicon vias.

By Ed Sperling
Semiconductor Manufacturing and Design sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; John Murphy, director of strategic alliances marketing at Cadence; Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics; Bob Smith, vice president of marketing and business development at Magma, and Linh Hong, vice president of marketing at Kilopass. What follows are excerpts of that conversation.

SMD: As we move to the next process node is multisourcing realistic? Everyone will have different processes and approaches and tools.
Murphy: Market segmentation is an important consideration here. If you look at the fab lite trend, it’s reaching the point where the early majority is adopting it. These are large companies that have owned fabs. There are about 15 of these companies.

SMD: You’re talking about companies such as Freescale and TI?
Murphy: Yes. Some are clinging to the old style of controlling everything even though they don’t actually own it. They want to control the libraries and the IP. That creates an infrastructure problem for them as well as increasing risk. If they’re trying to differentiate themselves around that, it makes sense to them. Other companies are saying that if they can’t differentiate themselves in hardware then they’re going to differentiate in software. There are a few nexus points. One is at the system level, where you make hardware-software tradeoffs. Another is at the IP level, where you select and maybe re-characterize IP quickly through some kind of engine blessed by the foundries. And then there are the hardcore semiconductor guys who want to control the process. If you take all three of these you get a representation of what’s coming at the very advanced nodes. Those are going to be hard and expensive to get to. The companies going to 20nm are mostly the processor guys, and they’re trying to control the process. The next guys will care about schedule, cost and risk. Schedule matters to everyone.
Buehler-Garcia: They also care about access to supply.
Murphy: That’s true. It’s access to supply, power, performance and area, and process because it’s all about compute performance. The next wave will be about schedule and risk, which is where you start considering multiple foundries. The early guys are going to partner with foundries because it’s so hard to get there. As that stabilizes, you’ll see a change.
Ng: I don’t agree. The lead guys have the largest volumes. They expect a very fast ramp in a very fixed market window. The discussions we’re having at 20nm involve a multisource strategy because they know their volumes are high and they do not want to be held hostage by any one manufacturer that may lock them in.
Buehler-Garcia: Is it really being held hostage? Or are they looking at this and saying, ‘Let’s be rational. If hit my number I will have 2.5 fabs of wafers. I’ve got to be able to break this out to multiple foundries so the risk to both of us is reasonable.’
Murphy: On that second wave, the processor guys look at a second source for precisely that reason.
Ng: It’s a supply assurance issue initially, but the later this goes on the more it becomes a cost issue. You’re trying to get a lower cost. If that’s the issue, then having to do a rip-and-replace doesn’t make any sense. That’s cost-prohibitive. That’s where you should look at where you can take the GDS II.
Hong: The reality is the world is getting smaller. There is so much consolidation going on that the big are going to get bigger and their volumes are going to get bigger. Being captive to a single foundry will not make sense for them. What worries me, though, are the mid-tier companies. Those with a couple hundred million dollars in revenue need a strategy to be competitive, and that’s also multi-foundry because it frees them from being captive to the pricing of a single foundry. They cannot develop all of the ecosystem and the IP themselves. There are quite of few tools out there that will do translation from one database to another to streamline the flow for a multifoundry strategy.
Buehler-Garcia: Those tools will get you started, but they won’t finish the job.
Ng: The midsize companies are caught in a vice grip because they don’t have the engineering resources to do the same design twice, but they also don’t have the business ROI to drive their process among different manufacturers. Many times they don’t even have the mindshare with EDA and IP companies to help them.
Buehler-Garcia: It depends on how your $300 million comes up. We have some customers that do 4.5 million to 5 million die per week with only two products, so that $300 million is for two products. That’s a big load on a foundry, especially if things tighten up. That’s an opportunity for the ecosystem to help them. But there’s another reason to help them, too. The lead guys hit the node hard, then after Christmas they drop it and move onto the next node. So you have $6 billion in fab infrastructure sitting idle. That’s not good for anyone. If we can help get the next wave in sooner, that’s good for all of us.
Smith: Looking past 20nm, my guess is we won’t have many companies. The big will get bigger, but what does that mean to the rest of the industry?
Ng: I think that is a challenge for the whole industry. That’s why you see most customers at the leading edge looking at 28nm or 20nm, but there are only a few designs that are even available for consideration. Even foundries are dropping off like flies because the next investment will be tens of billions of dollars. There will be fewer customers. They will continue, however, to drive the next process development. Those guys are getting larger, but the number of foundry players and the number of ecosystem players who will support these nodes will drop off. It’s an ROI game.
Smith: I can envision the industry going the other direction, too, so we’re all an integrated company again.
Ng: In the foundry business we’re always thinking about ROI. Even foundries and others in the supply chain will be forced to look at new business models on the cost side of it. The Common Platform alliance is a cost-sharing, best-of-mind development. Our cost of the next leading-edge node is one-seventh. That’s a strategic advantage. Other folks in the ecosystem will have to look at how you still deliver best-in-class solutions in a way that is economical and still allows you to be there.

SMD: What happens when we shift to 2.5D and 3D stacking? Does that change the dynamics of all of this?
Buehler-Garcia: It changes the flow. The supply chain is dropping off because of the cost of doing 20nm. The cost of building and supporting the number of decks and checks is a ton of people. But then the question comes back: ‘Does that mean that no one comes behind?’ Are there only three or four companies that go down to 20nm and all the IP with it? Or is it really about the gap between the first wave and the second wave, and we’re concerned that the second wave may not show up on time? They will show up eventually. We heard the industry was going to die at 90nm because of mask costs. We figure out a way to do it. But what has changed is the dynamic of when you hit the node because of ROI considerations. That’s where 2.5D and 3D come in. You can go up and still stay at the node you’re on.

SMD: Or you can buy a 20nm piece of logic and slap it onto 180nm analog, right?
Murphy: There are a number of challenges with 3D. It’s a technology enabler for a business model change, but if a piece of technology fails and it’s two tiers under a stack, how do you go get that? Or how do you make sure things will work before you put it together?

SMD: But it’s also harder with real 3D stacking than with 2.5D system-in-package, right?
Murphy: That’s true. The risk is still there with 2.5D, but with 3D it gets even more so. That’s an enabler for people to change how they integrate, and how IP is exchanged for value in the industry. Whether it’s delivered as a chip or soft IP or hardened IP, it gets integrated into a big SoC or stacked onto a 3D IC and allows semiconductor companies to have more flexibility in their business model. If you look at the risk in a 3D IC, but if it failed on your whole SoC it’s the same kind of risk. It’s just that the technology is new.
Buehler-Garcia: But 3D is another factor of multisourcing. If you really want to get a piece of flash memory, you buy it from the memory vendor. Why should I pay GlobalFoundries or TSMC for that bulk CMOS? But now you also have two sources of supply that you have to manage. It’s another factor you have to consider.
Murphy: It makes it more interesting. How big of a die can you yield at 90% versus how can you yield a module reliably with the right physical characteristics so it doesn’t overheat?
Buehler-Garcia: If you look at what Xilinx did with their 3D stack, at 28nm that would have been a 24 x 20 die size. If you just run the math on defect density, that’s a problem. If you split that into four tiles, at least you have a shot of getting it right. It’s not a long-term solution, but it is a strategy to get into the node and yield quicker. That’s an interesting tradeoff.
Ng: That’s exactly what it is. It’s trading off the current limitations of designing a 3D IC with the verification and packaging challenges vs. getting to acceptable defect density on larger die. The infrastructure for 3D is not mature, and standardization efforts are still ongoing. It’s a different way of looking at it. We don’t look at 3D as a way of dealing with legacy technology. The inquiries we get are at the leading edge. It’s an area we’re doing development in, but it has it’s own challenges.
Hong: Those challenges will have to be overcome. With the shift from high k/metal gate technology to FinFET to a new germanium or gallium arsenide substrate, that’s all happening too fast. There’s a lot of risk in all of those changes, along with new tooling and PDKs. That’s what makes 2.5D and 3D so promising. Your I/O’s don’t have to be in 20nm. And with DRAM and embedded flash, you can just have that on another die.
Buehler-Garcia: If it’s a non-standard process, then taking it off [the die] makes sense. If you get to 28nm you have plenty of die area. But when you talk about embedded flash and MEMS, that’s a lot to carry the die along when you’re only using 2% for that extra capability. From a technology standpoint it can be done, but the cost of that silicon isn’t worth it.

By Ed Sperling

Future memory technology inside of mobile devices will use less power and run faster at each rev of Moore’s Law, but that technology also will look different, use different materials, and will be manufactured with different equipment, processes and technologies.

While this technology will owe its heritage to research and testing of the past few decades, the differences are expected to be dramatic. A panel of vendors, their customers and researchers took a deep dive into the research that will change the memory market of the future at an IEEE International Memory Workshop held Monday in Monterey, Calif. The discussion, chaired by Raman Achutharaman, VP of strategy and marketing for Applied Materials’ silicon systems’ group, pointed to some interesting research, developments and future standards.

What’s next?
Laith Altimime, Imec’s program director for CMOS process technology, said that over the next decade memory makers will require new materials (graphene and/or carbon nanotubes, for example); new techniques, including EUV lithography, air gap insulation and 3D stacking with through-silicon vias; and new structures, including hybrid tunneling field effect transistors (TFETs), VFETs and TANOS cells.

“New materials and device architectures are the key,” said Altimime, noting that 3D stacking will “take over everything in its path.” That includes resistive RAM (RRAM), a non-volatile type of memory now in the research phase that relies on current applied to a filament; 1T-RAM, a higher-density version of RAM; and spin-transfer torque RAM, which changes the magnetization on a thin magnetic layer by running a spin-polarized current across it.

Altimime noted that scaling beyond 16nm most likely will require 3D cell architectures. He said the base material will still be CMOS, but it also will include higher-k dielectrics, metals, and stack engineering.

Fig. 1: Air gap insulation. Source: Applied Materials

NAND changes
Sung-Kye Park, of Hynix’s Memory R&D Division, noted that NAND will require a slew of changes to decrease charge loss and increase e-field retention. Those changes will include everything from air gap technology to an increased doping of the control gate. He expects new structures and new materials to start hitting the market within two years.

“3D flash is a possible candidate,” Park said, pointing to Toshiba’s pipe-shaped Bit Cost Scalable technology, Samsung’s Terabit Cell Array Transistor (TCAT), Hynix’s 3D-FG and hybrid chips. But he noted there also are potential hurdles in areas such as process integration, particularly in the areas of multistack deposition and word-line formation.

Fig. 2: 3D NAND architectures. Source: Applied Materials

DRAM shift
Joo Young Lee, strategic planning manager at Samsung, said the goal for DRAM is still a 35% cost reduction each year, but to achieve that will require moving to the next process nodes. DRAM is currently approaching 30nm, he said. He expects it to hit 25nm by 2015 and 14nm by 2020, with DDR4 hitting mainstream in 2013. EUV will be required at 14nm, he said.

Reaching those advanced nodes will require changes in some of DRAM’s basic structures—cell capacitors, cell array transistors and cell node contacts, all of which will need to be re-engineered.

Patterning issues
Yoshitaka Tsunashima, a leading researcher at Toshiba, said his company’s NAND technology already requires double patterning. At 14nm, double patterning and EUV both will be required.

EUV has its own issues, of course—light source performance, mask defect control, optical performance, mask data preparation, and resist performance. But he noted that 11 companies are now working to solve those issues as part of the EUV Infrastructure Development Engineering Center (EIDEC).

“The other way we can get there is 3D NAND,” he said, noting that either approach—lithography or stacking—or both will help reduce bit costs. He said that technology also can be extended to RRAM, organic memory and MEMS memory.

Customer view
Nokia’s Matti Floman said the ideal solution would be universal memory. But given that is an unlikely development, what’s needed from his company’s standpoint are higher bandwidth for DRAM and non-volatile memory, new package solutions, lower power consumption, higher temperature tolerance, pre-developed scalable modules, and standard solutions.

He noted that Wide I/O is seen as a strong candidate for replacing DDR2 and DDR3 in high-end products. Mass memory, meanwhile, is moving toward NAND and embedded MultiMediaCard (eMMC).

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general manager of the Fab Analysis Business Unit at Magma Design Automation. What follows are excerpts of that conversation.

SMD: Does a shortened time-to-market deadline require more DFM or less?
Tabery: If it’s so short, then the ramp is just as important. The ramp is usually proportional to peak yield.
Benware: That’s why we’re addressing the cycle time for implementing DFM. It’s real-time verification while you’re drawing the polygons. But when we implemented that, the customers used the extra time to do more DFM. They didn’t change the tapeout time. As you improve DFM, you see people doing more within that window. The other challenge is that you have all these rules, but it’s hard to quantify which ones you should do. How much will your yield change if you follow a particular rule?
Tabery: It’s expensive to do it. So it comes back to the same cost question. There is uncertainty in DFM rules. The base rule is 20 and we’re debating for the DFM rule to be 26 or 28. We’re thinking about characterizing that slope of yield versus closure. But you’re talking about parts-per-billion failure rates, so you need to make billions and billions of these vias to check whether that adds 1% yield and it isn’t worth it or whether it adds 10% yield and it is worth it. Characterizing that roll-off curve is fundamental. But how do you bring those all together to have a useful model and to be able to synthesize that into a design rule. Uncertainty is expensive, but it’s also expensive if you can’t get your yield up faster. Both inspection and the EDA community can help us determine whether it should be 26 or 28 for that recommended rule.

SMD: From the equipment side, is there more influence from the design side or the foundries as we move to advanced nodes?
Conley: I’m not sure it changes. The restrictive design rules today involve the pitches in logic to make them more uniform. These are gridded design rules. This helps inspection because everything becomes uniform. The tools can find the defects more easily. The challenge we see is the complexity of recipe creation, which is why we are bringing design into the fabs. The foundries have a huge number of products and they do need to inspect every product because each product is from a different fabless company. They need to create a recipe for every product. They have numerous memory areas, and these can be identified ahead of time if we have the design built. This is what we’re doing with Magma.
Oberai: The users don’t want recipe creation as a manual process anymore. It’s too complex. They want some correlation to design geometries for incoming designs. They have to create hundreds and hundreds of recipes.

SMD: How does 3D stacking affect yield?
Conley: It’s a totally new game. You invest all the cost in working die, and you have two or more working die, and in the process of stacking you can encounter problems and lose everything.
Benware: The biggest challenge in 3D stacking is in test. How are you going to test these devices and make sure that two devices that were tested independently will work when you bring them together? And once you bring them together, how do you test each device individually. The challenge isn’t yield. It’s test to get to yield.
Tabery: We have packaging yield. We have models for that to know how it works. Putting two chips together is another process step and you have to understand the yield for that, but the yield targets would be very high because it’s using die that are already qualified and tested. The testability of that is interesting. How many TSVs do you need to test?
Oberai: We are seeing more and more of that. We are moving from die- or wafer-level navigation to board-level navigation. We put the whole board in a TM. Customers want to test the whole board. You test what the interconnectivity is. There are software capabilities to model this. It includes leakage and durability of connectors and what are the other effects of powering up the whole board or stacked die. But there isn’t anywhere near the level of tools for stacked die that we have on a single die.

SMD: There’s also a push to thin out the wafers in stacked die. How do you deal with that?
Tabery: It’s thinned out after the processing, so the impact on wafer processing is small. But there are additional mechanical and packaging challenges.
Oberai: It’s more the mechanical aspects.

SMD: Doesn’t that create more defects?
Tabery: It certainly could. You polish on the back side so that’s less risky, but if you induce a crack or there’s new stress that isn’t modeled, you need to understand that. The TSVs cause huge stress fields around the transistors. If the ones to the right of the TSV are slow but the ones just above the TSVs are fast, that’s no good.

SMD: 3D also blurs the lines across the supply chain. Who’s responsible for problems in complex chips and how do you deal with these problems?
Conley: The partnership between Applied Materials and Magma is part of this answer. There needs to be more partnerships between companies to solve critical issues. You need to take the advantages of each company and try to creation solution that is greater than the sum of both parts.
Oberai: In our partnership we are the ones creating the framework for the data depository and correlation and creating recipes and then sending it to the tool. The onus is on us to make sure the recipe generation has taken into account all the different elements. But we are heavily reliant on the tool providing all the parameters. Hopefully, when that happens there is alignment. We build a golden-case model to run sample recipes. If the recipe works we need to calibrate how long before we need to model again. The collaboration between companies is critical. The timekeeper is the customer or the fab. There are a lot of metrology tools and they are signaling these things. You never saw this kind of cooperation before. The onus is on all sides. There is enough harmony in this business to make this work. This is going to be an incremental process, though.
Benware: There’s a requirement for more interaction. We have to partner with our customers to be successful. While we see that test, manufacturing and design need to be linked, where we see the biggest challenge is in ownership of data. Somebody owns the data and someone else needs that data. Between the fabless company and the foundry, on the design side you have all this data and that needs to go to the fab somehow so they can do their process tuning and inspection based on the design. And it’s no longer just GDS. There are parametric and timing issues, so there’s more design data that has to go. At test you collect a whole bunch of failure data. Who owns that data? Someone had to take the wafer and scrap the wafer. Who owns that scrap wafer? Once you have the test data, you have to do yield analysis and that’s design information again. The fabless company owns the design information but it’s the fab that has the result. Where the data exists and how to transfer it between companies between exists today.

SMD: Isn’t that a mindset change?
Benware: Yes. There are IP concerns, too. Even if the data is encrypted, people don’t trust the encryption. And it’s multinational, so there are concerns with that. Even though vendors are providing these kinds of capabilities, one of the biggest challenges to the industry adopting it are overcoming IP and data-sharing hurdles that people are slow to solve.
Oberai: Even if there is a defect the foundry won’t give us the defect. You have to go down and look at it. They think, ‘What if it has something to do with a design customer?’ There’s not much you can do with a defect. But there are a lot of constraints on data.
Benware: A few years back we were seeing a lot of resistance to adopting diagnosis and volume at fabless customers because they couldn’t figure out who would pay for the tools and who would use the data. Over the past few years we’ve seen that perception of an IP issue completely evaporate when there is a yield problem. These companies are sending the foundry absolutely everything. They don’t want to put anything in place ahead of time, but when the problem comes it’s like grease. People have experienced that enough that they’re starting to overcome their issues. That’s a testament that yield is a big problem and the foundry and the fabless companies are in this together.
Oberai: It’s all about yield.

By Ed Sperling
Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta. What follows are excerpts of that roundtable discussion.

SMD: How important will standards be in 3D?
Radojcic: We definitely need standards. But before the world invents standards we have to have a pretty good image of what we’re doing. With Wide I/O memory that was easy. JEDEC was developing the standard so it was all good. If you open the door for logic on logic, it’s not going to be seamless. You really need to think about what kind of partitioning makes sense. You’re not going to want to split your clocks. We first need to do that as an industrial community.
Wingard: In the logic-on-logic space it’s going to be a closed shop model first. It’s going to be the same people designing the chip above and below.
Subramaniam: Yes, they will have control of the area and the design. The other place I see logic working is in re-use. A company could build the building blocks and then use those building blocks for different applications. Again, that will be a closed-shop approach.
Wingard: Then you need standards. Everytime you mention re-use you will need a standard.
Subramaniam: At least you will need an internal standard.
Wingard: One thing that’s different about the way we’ve done packaging before is that we had a layer of the package in between that had the same protocols and signaling levels even though our bond patterns didn’t match exactly. We relied on PCBs to make things match. With TSVs we don’t have that anymore. You have to agree on everything, from pad pitch to signaling all the way up that stack.
Radojcic: And it’s all interdependent. Figuring it out is a big problem.
Wingard: That’s what makes interposers so interesting. They’re the bridge for things like logic on logic. I think 2.5D logic on logic will happen well before 3D logic on logic for exactly these reasons.
Radojcic: For companies that can tolerate the form factor.
Wingard: Yes.

SMD: Isn’t one of the big issues focused on responsibility? You may have two perfectly good chips, but when they’re put together they don’t work properly.
Radojcic: There are things before that we need to figure out. We need information from the memory guys for stacking memory on logic so you can manage your hotspots and mechanical interaction. We need to agree how we exchange information between us and what that information includes. Then, when it comes to the building side, we need to create a supply chain business model for who owns what.
Hogan: This isn’t trivial. It’s a lot of work and we will solve it. But why bother? Let’s back out for a moment. The SoC is the way everyone delivers system value today. That’s dominated by the ARM processor. Everyone uses something that looks like an interconnect. On that interconnect people differentiate themselves with two things. One is a peripheral device. Texas Instruments is a great example of that. Someone else might add memories. The second thing is software. What 3D allows you to do is consider other things and other arrangements. We can spend a lot of time talking about the margins on SoCs, but they’re 50% or 60%. That’s why everyone does SoCs instead of discretes. There’s more value in the system. There will be a lot more integration of peripheral devices and software. That’s what’s exciting about this. It’s not to trivialize all the EDA work and the supply chain, because there’s a lot of work, but that’s what’s really interesting for me. This will allow more democratization of a design.
Gianfagna: You were talking about how the ecosystem would evolve. First it would be monolithic and internal by one company. Then you try to figure out how you do re-use, and then there will be third parties. That’s exactly how the existing 2D ecosystem evolved. That’s depressing. It says we didn’t really learn anything from 2D. You don’t think we’re any smarter?
Wingard: We’re starting with the standard interface stuff. Logic on memory is the early example. It’s not a closed shop today.
Subramaniam: It is a closed shop. Samsung owns the processor and the memory. They already do this Wide I/O design. They’re not going to wait for the standard. There will be a standard eventually, but they’re going to drive it.
Wingard: My guess is that’s not the volume driver. It’s a technology-proving vehicle. But independently, it will be standard interface first, then logic-on-logic in a closed environment, then we’ll figure out what else we can standardize on. To think that we’re going to get standardization ahead of where people know how to use it is very scary.
Gianfagna: So we’re stuck with standards driving the ecosystem and not the other way around?
Hogan: Anytime you have standards in place you lower the barrier to entry. That accelerates the ability of the ecosystem to grow. But there will be companies like Samsung that can’t wait, so they’re going to do their own version. And they have enough volume to do it. For the rest of the world they’ll have to wait for this chip-to-chip and logic-to-logic capability. But it will happen.
Subramaniam: On the logic-to-logic, I’m still not convinced a standard will evolve. The reason why a Wide I/O standard evolved was that you need a third party. Nobody is going to be designing their own memory. A third party is necessary. But with logic on logic, people may view it as a competitive advantage not to have a standard. There’s no reason, if I develop my own logic-on-logic, that it should hook up with a third-party logic design. I’m not agreeing with logic on logic becoming a standard.
Gianfagna: At one level that’s true. People don’t want to be homogenized.
Hogan: At CES Microsoft said it was going to use an ARM-based SoC with an Nvidia block. An Nvidia block? If you think about Xbox development they started out doing everything themselves, then they gave up and went to ARM. They’re not even doing their own graphics processor anymore.
Wingard: PoP (package-on-package) has been about memory on logic. One common version is baseband on application processor. Right now that business is done partly because some of the companies don’t have their own baseband assets. I would expect that to be logic-on-logic in the future. The more advanced basebands need more access to memory than they did before. There’s going to have to be some reasonable baseband connectivity in the future. Even if there aren’t any industry standards, with logic on logic if you want to get any re-use you’re at least going to need company standards.
Gianfagna: You guys are debating whether you integrate IP blocks on one die or two. You’re going to start with a certain number of building blocks. But if you have one at 22nm and one at 65nm, how do you connect them?
Wingard: I don’t think the model for a long time will be, ‘I’ve got this system to go build and I’m going to partition it across a set of dies the way I partition it across a set of FPGAs.
Gianfagna: Why?
Wingard: Because of legacy and because it’s too expensive. With legacy I’ve got something that’s been proven. But I’ve got something else I want to change, so this other die is the one with the new stuff on it. It’s that kind of re-use and how systems evolve and not having the assets because this thing comes from somebody else. All the logic doesn’t have to end up on one die.
Radojcic: There are many new constraints, both physical and architectural. The idea is that you take one die and slap it together with another die. But when you start thinking about it more and more it makes your head hurts. There are all these degrees of freedom that are interdependent.
Hogan: If I’m Cisco, I’ve got 35 million lines of legacy code I have to run in my router. How do I upgrade? It would be great to have an interposer because I can leave all that old code. Routers, servers and base stations are going to be loving this. The mil/aero guys are going to love this, too.
Subramaniam: If you have a 28nm chip, your upgrade could be done with an older chip geometry, and then you can use an interposer to slap the two together. Your equipment and design costs are going to be much lower with this approach.

SMD: There are two trends here. One is to build more and more on the SoC. The other is to set up all these separate processors. Does 3D move it all into one device and does it become more of a logical partitioning problem?
Gianfagna: Yes, but it’s going to happen slowly. You’ve taken what used to be on a printed circuit board and integrated it into a device. The more planes you add, the opportunities to mess up go up exponentially around thermal, stress, mechanical, heat dissipation, TSVs that don’t have anything to do with an interconnect. You can think about integrating multiple pieces of the system in the same package, but it’s going to take a while to get there.
Hogan: If you’re talking about integrating silicon, try getting TSMC to add two more mask layers or two more stops as the wafer travels around the fab. You need an enormous amount of volume because they like to minimize risk. Otherwise you’d need your own fab.
Subramaniam: If you put a TSV on a chip you’re effectively creating three or four layers on top of your 10 layers of metal. That’s going to happen sooner or later. The question is how many more layers will you get. There will be a limit.
Hogan: When we did studies on SiP (system in package), the yield is a linear function with the number of layers. Every time you add another layer it’s worse yield.
Subramaniam: But these layers are very coarse.
Hogan: I understand, but what should your yield be? How do you even test these things. The system is only functional when you have both die together.
Subramaniam: And you cannot use wirebond.
Gianfagna: You might also get a really fancy boundary scan and isolation logic.
Radojcic: We’re having a discussion the 3D industry already went through. The first discussion was, ‘This is really cool.’ The next discussion was, ‘How am I going to do this? How am I going to test this?’ The classic hype curve has been followed. There is a trough of disillusionment. But some of these things are already solved or solvable. It’s good to focus on, ‘We can do this. We can do memory on logic. So let’s focus on the work to be done.’ The work that’s left to be done is design exchange formats so you can model thermal or stress behavior from die A to die B, and you need feed power from tier two to tier one. We just need to get our act together and create standards.
Hogan: If you have standards in place you can get things done. If you have to integrate this stuff, no one lets the standards out and you have to fight for them—or you get competing standards.