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Posts Tagged ‘3D integration’

Packaging Conference Addresses Challenges, Opportunities in New Technologies

Friday, December 18th, 2015

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By Jeff Dorsch, Contributing Editor

On the second day of the 12th annual 3D ASIP conference, the heavy hitters came out to talk. Attendees heard presentations from executives of Amkor Technology, the Defense Advanced Research Projects Agency (DARPA), Northrop Grumman, Taiwan Semiconductor Manufacturing, Teledyne Scientific & Imaging, and Xilinx, among other companies.

The day began with Pioneer Awards presented to Mitsumasa Koyanagi of Tohoku University and Peter Ramm of Fraunhofer EMFT. Those two men then gave talks on their involvement in 3D packaging technology over the decades.

“It started with DRAM in 1974,” Koyanagi recalled.

Ramm reviewed various European initiatives in the field, including the development of InterChip Vias (ICVs), a precursor to through-silicon via (TSV) technology, and the concept of known good die.

Suresh Ramalingam of Xilinx discussed the attributes of Silicon-less Interconnect Technology (SLIT), which the chip company developed in cooperation with Siliconware Precision Industries (SPIL), the IC assembly, bumping, and testing contractor.

“It’s still a silicon platform,” he pointed out. SLIT promises to connect multiple die in a package without resorting to TSVs. “Wafer warpage is a big issue,” Ramalingam noted.

Amkor’s Mike Kelly followed Ramalingam. “There’s a kind of upturn or resurgence in 2.5D, driven by high-bandwidth memory,” he said.

Amkor is offering the Silicon-less Interposer Module (SLIM) as its TSV alternative technology, according to Kelly, while also providing Silicon Wafer Integrated Fan-out Technology (SWIFT) as another packaging alternative to TSV-based interconnections.

KC Yee of TSMC, filling in for an absent presenter, spoke at length about the foundry’s Integrated Fan-Out (InFO) wafer-level packaging technology. “InFO eliminates silicon, TSVs, interposers,” he said. At the same time, InFO “reduces cost,” he asserted.

DARPA’s Daniel Green spoke about the agency’s Diverse Accessible Heterogeneous Integration (DAHI) program, which succeeded its Compound Semiconductor Materials on Silicon (COSMOS) program.

He was followed by Augusto Gutierrez-Aitken of Northrop Grumman Aerospace Systems. “DAHI is not in competition with CMOS,” he said. NGAS is developing a foundry for heterogeneous integration projects, inviting in companies and universities to participate in the research and development.

Teledyne Scientific’s Miguel Urteaga spoke about his company’s CS-STACK 3D stacking chip program. “We’re looking to get the highest III-V performance we can,” he said.

Blog review December 16, 2014

Tuesday, December 16th, 2014

Maybe, just maybe, ASML Holding N.V. (ASML) has made the near-impossible a reality by creating a cost-effective Extreme Ultra-Violet (EUV @ ~13.5nm wavelength) all-reflective lithographic tool. The company has announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has ordered two NXE:3350B EUV systems for delivery in 2015 with the intention to use those systems in production. In addition, two NXE:3300B systems already delivered to TSMC will be upgraded to NXE:3350B performance. While costs and throughputs are conspicuously not-mentioned, this is still an important step for the industry.

The good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2014 IEEE International Electron Devices Meeting. Dick James of Chipworks writes that it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

The 4th Annual Global Interposer Technology Workshop at GaTech gathered 200 attendees from 11 countries to discuss the status of interposer technology. It has become the one meeting where you can find all the key interposer layers including those representing glass, laminate and silicon, blogs Phil Garrou.

Sharon C. Glotzer and Nicholas A. Kotov are both researchers at the University of Michigan who were just awarded a MRS Medal at the Materials Research Society (MRS) Fall Meeting in San Francisco for their work on “Integration of Computation and Experiment for Discovery and Design of Nanoparticle Self-Assembly.”

In order to keep pace with Moore’s Law, semiconductor market leaders have had to adopt increasingly challenging technology roadmaps, which are leading to new demands on electronic materials (EM) product quality for leading-edge chip manufacturing. Dr. Atul Athalye, Head of Technology, Linde Electronics, discusses the challenges.

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. Adele Hars reports.

Does your design’s interconnect have high enough wire width to withstand ESD? Frank Feng of Mentor Graphics writes in his blog that although applying DRC to check for ESD protection has been in use for a while, designers still struggle to perform this check, because a pure DRC approach can’t identify the direction of an electrical current flow, which means the check can’t directly differentiate the width or length of a wire polygon against a current flow.

At the recent IMAPS conference, Samsung electro-mechanics compared their Plated Mold Via Technology (PMV) to the well known Amkor Through Mold Via  (TMV) technology. The two process flows are compared. Phil Garrou reports.

3D ASIP: “It’s Complicated”

Monday, December 15th, 2014

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By Jeff Dorsch, Contributing Editor

The presentations at this week’s 3D Architectures in Semiconductor Integration and Packaging conference could be summed up in a famous Facebook status: “It’s complicated.”

They also could be summed up in one word: Progress.

This year has seen tremendous progress in implementation of 3DIC technology, according to speakers at the 11th annual conference, held in Burlingame, Calif. Those who have been touting and tracking 3D chips for years are looking forward to the 2015 introduction of Intel’s Xeon Phi “Knights Landing” processor for high-performance computing, which will incorporate the Hybrid Memory Cube technology in the same package as the CPU.

Activities began Wednesday, December 10, with a preconference symposium on “2.5/3D-IC Design Tools and Flows” and “3D Integration: 3D Process Technology.” Bill Martin of E-System Design kicked off the program with a presentation on path finding, a topic addressed several times over the next two days. He emphasized that preparing for a chip design project, such as choosing the right tools, is as important as the design and implementation phases when it comes to embracing 3DIC technology.

John Ferguson of Mentor Graphics later said there is “an infrastructure problem” in the semiconductor industry when it comes to process design kits (PDKs) for 2.5D and 3D chips. Taiwan Semiconductor Manufacturing has collaborated with Mentor and other leading suppliers of electronic design automation tools to offer PDKs to TSMC foundry customers, yet the next step must be taken to have outsourced semiconductor assembly and test contractors provide packaging PDKs.

Phil Garrou, a senior consultant for Yole Developpement, said 2014 has witnessed significant progress in implementation of 3DIC technology. “We no longer need to prove performance,” he said. “The remaining issue is cost.”

Several speakers addressed the topic of the Internet of Things and how it involves 3DICs on the first day of the conference. Steven Schulz of the Silicon Integration Initiative (Si2) said 3D chip designers should think of their products not as system-on-a-chip devices, but system-on-a-stack.

Yole’s Rozalia Beica said predictions that the Internet of Things market will be worth trillions of dollars in 2022 are “overoptimistic” and that “optimism is higher than current investment.” Yole looks for the market in IoT sensors to be worth $400 billion in 2024, she said.

Samta Bonsal of the GE Software Center spoke on the Industrial Internet. “That world is huge,” she said, and predicted it will have “a bigger impact” than consumer-oriented IoT applications. Gartner says the market for all IoT chips will be worth $7.58 billion in 2015, she noted. The market research firm also forecasts that 8 billion connected devices will be shipped during 2020, encompassing 35 billion semiconductor devices produced on 6 million wafers.

E. Jan Vardaman of TechSearch International presented a lively review of 3DIC technology, past and present. “There’s been a lot of good progress with TSV (through-silicon vias), enabling us to improve the process,” she said. Still, 3DIC has been a long time in coming, noting that Micron Technology began research and development on DRAM stacking a dozen years ago and Xilinx initiated development of a silicon-based interposer to be used with TSVs in 2006, six years before it was able to offer a field-programmable gate array with such technology, manufactured in volume by TSMC.

Dyi-Chung Hu of Unimicron looked past the silicon interposer to the era to using glass for interposers and substrate core materials. Glass has a low coefficient of thermal expansion compared with silicon, he noted, and is very flat. Its chief drawback is its brittleness, according to Hu.

Michael Gaynes of IBM’s Thomas J. Watson Research Center reported on his company’s two ICECool projects for the Defense Advanced Research Projects Agency, developing 3DICs that could run cooler in data-center servers.

The last day of the conference coincided with a convention devoted to the Star Trek television series in the adjacent hotel ballroom. Attendees dressed as Klingons and starship crew members mingled with the 3DIC technologists in the hotel lobby, all dreaming and thinking about the future.

Monolithic 3D breakthrough at IEEE S3S 2014

Monday, September 15th, 2014

By Zvi Or-Bach, president and CEO of MonolithIC 3D

In the upcoming 2014 IEEE S3S conference (October 6-9), MonolithIC 3D will unveil a breakthrough flow that is game-changing for 3D IC. For the first time ever monolithic 3D (“M3DI”) could be built using the existing fab and the existing transistor flow.

The IEEE S3S 2014 is the first conference to focus on the emerging monolithic 3D technology in addition to focuses on SOI and sub-threshold technologies. It is the conference to learn and get updated on these technologies and on M3DI, which is that newest part integrated into the conference. The 3D part of S3S 2014 will have a full day of tutorial presentations by leading researchers in the space, a full session of invited papers, and will conclude with a session dedicated to discussing the most recent breakthroughs in the field.

The M3DI short course will cover alternative process flows that enable M3DI, discuss the challenges and solutions to removal of the operating heat of monolithic 3D stacks, and describe the range of powerful advantages provided by M3DI. Subsequently, Prof. Sung Kyu Lim of Georgia Tech will cover EDA for M3DI. This will be followed by broad coverage of M3DI for memory applications by two leading experts in the field, Akihiro Nitayama of Toshiba/Tokohu University and Deepak Sekar of Rambus. M3DI provides unparalleled heterogeneous integration options, which will be covered by Prof. Eugene Fitzgerald of MIT and SMART Lee Institute of Singapore. He will be describing the integration of silicon with other crystals for electro-optic device integration.

A GaN+CMOS power amplifier design using the integrated foundry PDK.

The short course will conclude with Prof. Philip Wong of Stanford, who leads research efforts to integrate silicon with carbon nanotube and advanced 2D transistors layered with memory such as STT-MRAM and RRAM.

In the special invited 3D Hot Topics session we expect to get a full spectrum of the latest progress in the field. Particularly worth noting is the recent progress on the work done by CEA Leti with involvement of ST Micro, IBM and supported by Qualcomm. This work shows both a practical path to monolithic 3D IC and cost analysis of the monolithic 3D advantages. The following chart illustrates the reasons for the high interest in the technology.

On Thursday afternoon, in the 3D New Developments session, a game changing breakthrough technology will be presented. Leveraging the breakthrough progress in wafer bonding technology, presenting for the first time ever a monolithic 3D flow using existing fab transistor process. Any fab could utilize this breakthrough to provide far better products at minimum capital and R&D investment. This game changing flow removes the historical differentiation between sequential and parallel 3D, and should significantly reduce the cost and the time for monolithic 3D adoption throughout the semiconductor industry.

Late News for 3DIC will feature CEA Leti presenting a fully constructed M3DI SOI device, and IBM will discuss its Multi Stacked Memory Wafer technology.

More information is available on the conference site: S3S Conference 2014

Qualcomm: Scaling down is not cost-economic anymore – so we are looking at true monolithic 3D

Monday, June 16th, 2014

By Zvi Or-Bach, President and CEO of MonolithIC 3D Inc.

Over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.

Karim Arabi, Qualcomm VP of Engineering, voiced the strongest support and provided many details of monolithic 3D’s role, in his keynote at this year’s DAC. A good summary was posted at the Tech Design Forums site under the title “3D and EDA need to make up for Moore’s Law, says Qualcomm.” In this blog, I’ll highlight some of the very interesting quotes from Arabi’s keynote: “Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase. One of the biggest problems is cost. We are very cost sensitive. Moore’s Law has been great. Now, although we are still scaling down, it’s not cost-economic anymore”

Qualcomm is not the only fabless company voicing its concern with cost. Early in 2013 Nvidia said it is “deeply unhappy” and executives of Broadcom followed suite. The following chart, presented by ARM, illustrates it nicely.

But it seems that the problem is even more severe than that. In our blog Moore’s Law has stopped at 28nm we examined the expected increase of SoC cost due to poor scaling of embedded SRAM (eSRAM). We should note that the chart above, like many others, is about the cost per transistor associated with dimensional scaling. Escalating lithography cost causes escalating wafer cost, which neutralizes the 2X transistor density increases.

Yet eSRAM scales far less than 2X and, accordingly, for most SOCs, scaling would be even more costly. This issue has been confirmed again with the recent VLSI 2014 paper “10-nm Platform Technology Featuring FinFET on Bulk and SOI” by Samsung, IBM, STMicroelectronics, GLOBALFOUNDRIES and UMC. They presented that the size of their 10nm bitcell is 0.053 µm², which is only 25 percent smaller than the 0.07 µm² reported for 14nm bitcell size. One should expect that an additional area penalty would occur for effective use in large memory blocks, as reported even for 14nm, which could bring the effective SRAM scaling to only about 15 percent, a long way from the 50 percent required to neutralize the escalating wafer costs.

However, cost is not the only issue that forced Qualcomm to consider monolithic 3D. Quoting Arabi:

“Interconnect RC is inching up as we go to deeper technology. That is a major problem because designs are becoming interconnect-dominated. Something has to be done about interconnect. What needs to be done is monolithic three-dimensional ICs. Through-silicon vias and micro bumps are useful where you need I/Os … But they are not really solving the interconnect issue I’m talking about … So we are looking at true monolithic 3D. You have normal vias between different stacks. Then interconnect lengths will be smaller than with 2D. If we can connect between layers the delay becomes smaller.”

The interconnect issue was also addressed at IEDM 2013 by Geoffrey Yeap, Qualcomm VP of Technology, in his invited talk:

“As performance mismatch between transistors and interconnects continue to increase, designs have become interconnect-limited. Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.”

Yeap provided the following chart for the growing gap between transistor delay and interconnect delay:

Arabi DAC 2014 keynote was also reported on Cadence’s website, which provides our final Arabi quote for this blog: Qualcomm is looking at “monolithic” 3D-ICs that use normal vias between stacked dies. This can provide a one-process-node advantage along with a 30 percent power savings, 40 percent performance gain, and 5-10 percent cost savings.

Clearly, monolithic 3D integration has a very important role in the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3DIC, and researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

Research Alert: May 13, 2014

Tuesday, May 13th, 2014

SRC and UC Berkeley pursue a more cost effective approach to 3D integration

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

The research focuses on integrating extra layers of transistors on a vertically integrated 3D monolithic chip using printing of semiconductor “inks” as compared to the current method of chip-stacking through 3D interconnect solutions.

The new process technology could help semiconductor manufacturers develop smaller and more versatile components that are less expensive and higher performing by enabling cost-effective integration of additional capabilities such as processing, memory, sensing and display. The low-temperature process is also compatible with polymer substrates, enabling potential new applications in wearable electronics and packaging.

To fabricate such devices, new material and process methodologies are needed for depositing nanoparticles for semiconductors, dielectrics and conductors. The research is particularly focused on solution-based processing due its low temperature compatibility with CMOS metallization as well as the potential for lower cost manufacturing.

“Initial results from the Berkeley team show that reasonably high performance can be obtained from ink-jet printed devices with process temperatures that are compatible with post-CMOS metallization, thus enabling a new route to monolithic 3D integration,” said Bob Havemann, Director of Nanomanufacturing Sciences at the SRC.

SEMATECH reports higher dose sensitivity progress in novel photoresist platforms

SEMATECH announced today that researchers have reported progress which could significantly improve resist sensitivity by incorporating metal oxide nanoparticles for extreme ultraviolet (EUV) lithography, bringing the technology another step toward enabling the development of high performance resists required to enable EUV for high-volume manufacturing (HVM).

SEMATECH engineers, in association with scientists from Cornell University, have demonstrated significantly higher dose sensitivity by incorporating metal oxide nanoparticles, with a resolution dose that is less than one fifth of that normally used with EUV scanner throughput calculations. These significant advances are critical in moving forward the infrastructure that will prepare EUV lithography for HVM at 20nm half-pitch.

“These resist platforms have the potential to significantly relax the EUV source power requirements to enable high-throughput EUV lithography—which has been the most critical barrier to enabling EUV to enter high-volume manufacturing,” said Michael Lercel, SEMATECH’s senior director of Technology. “With these disruptive photoresist platforms, SEMATECH is working toward enabling breakthrough high performance resists that move forward the infrastructure that will prepare EUV for cost-effective manufacturing.”

Taking the lead out of a promising solar cell

Northwestern University researchers are the first to develop a new solar cell with good efficiency that uses tin instead of lead perovskite as the harvester of light. The low-cost, environmentally friendly solar cell can be made easily using “bench” chemistry — no fancy equipment or hazardous materials.

“This is a breakthrough in taking the lead out of a very promising type of solar cell, called a perovskite,” said Mercouri G. Kanatzidis, an inorganic chemist with expertise in dealing with tin. “Tin is a very viable material, and we have shown the material does work as an efficient solar cell.”

Kanatzidis, who led the research, is the Charles E. and Emma H. Morrison Professor of Chemistry in the Weinberg College of Arts and Sciences.

The new solar cell uses a structure called a perovskite but with tin instead of lead as the light-absorbing material. Lead perovskite has achieved 15 percent efficiency, and tin perovskite should be able to match — and possibly surpass — that. Perovskite solar cells are being touted as the “next big thing in photovoltaics” and have reenergized the field.

Kanatzidis developed, synthesized and analyzed the material. He then turned to Northwestern collaborator and nanoscientist Robert P. H. Chang to help him engineer a solar cell that worked well.

“Our tin-based perovskite layer acts as an efficient sunlight absorber that is sandwiched between two electric charge transport layers for conducting electricity to the outside world,” said Chang, a professor of materials science and engineering at the McCormick School of Engineering and Applied Science.

Their solid-state tin solar cell has an efficiency of just below 6 percent, which is a very good starting point, Kanatzidis said. Two things make the material special: it can absorb most of the visible light spectrum, and the perovskite salt can be dissolved, and it will reform upon solvent removal without heating.

“Other scientists will see what we have done and improve on our methods,” Kanatzidis said. “There is no reason this new material can’t reach an efficiency better than 15 percent, which is what the lead perovskite solar cell offers. Tin and lead are in the same group in the periodic table, so we expect similar results.”

Perovskite solar cells have only been around — and only in the lab — since 2008. In 2012, Kanatzidis and Chang reported the new tin perovskite solar cell with promises of higher efficiency and lower fabrication costs while being environmentally safe.

“Solar energy is free and is the only energy that is sustainable forever,” Kanatzidis said. “If we know how to harvest this energy in an efficient way we can raise our standard of living and help preserve the environment.”

The solid-state tin solar cell is a sandwich of five layers, with each layer contributing something important. Being inorganic chemists, Kanatzidis and his postdoctoral fellows Feng Hao and Constantinos Stoumpos knew how to handle troublesome tin, specifically methylammonium tin iodide, which oxidizes when in contact with air.

The first layer is electrically conducting glass, which allows sunlight to enter the cell. Titanium dioxide is the next layer, deposited onto the glass. Together the two act as the electric front contact of the solar cell.

Next, the tin perovskite — the light absorbing layer — is deposited. This is done in a nitrogen glove box — the bench chemistry is done in this protected environment to avoid oxidation.

On top of that is the hole transport layer, which is essential to close the electrical circuit and obtain a functional cell. This required Kanatzidis and his colleagues to find the right chemicals so as not to destroy the tin underneath. They determined what the best chemicals were — a substituted pyridine molecule — by understanding the reactivity of the perovskite structure. This layer also is deposited in the glove box. The solar cell is then sealed and can be taken out into the air.

A thin layer of gold caps off the solar-cell sandwich. This layer is the back contact electrode of the solar cell. The entire device, with all five layers, is about one to two microns thick.

The researchers then tested the device under simulated full sunlight and recorded a power conversion efficiency of 5.73 percent.

Solid State Watch: May 2-8, 2014

Friday, May 9th, 2014
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The Week in Review: May 9, 2014

Friday, May 9th, 2014

SEMATECH announced this week that researchers have reached a significant milestone in reducing tool-generated defects from the multi-layer deposition of mask blanks used for extreme ultraviolet lithography, pushing the technology another significant step toward readiness for high-volume manufacturing.

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

GlobalFoundries this week introduced an optimized semiconductor manufacturing platform aimed specifically at meeting the stringent and evolving needs of the automotive industry.

Peregrine Semiconductor announced shipment of the first RF switches built on the UltraCMOS 10 technology platform.

BASF inaugurated a new Electronic Materials Sampling and Development facility in Hillsboro, Oregon. The new facility is a strategic step towards establishing a North American footprint to supply materials for semiconductor manufacturing applications related to the electronics industry.

Veeco Instruments Inc. has appointed Shubham Maheshwari, 42, as its new Executive Vice President, Finance and Chief Financial Officer (CFO). Mr. Maheshwari replaces David D. Glass, who announced his retirement from Veeco last December.

Avago Technologies Limited and LSI Corporation announced Avago has completed its acquisition of LSI Corporation for $11.15 per share in an all-cash transaction valued at approximately $6.6 billion.

Microchip Technology Inc., a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, this week introduced a new parallel Flash memory device.

The Semiconductor Industry Association announced that worldwide sales of semiconductors reached $78.47 billion during the first quarter of 2014, marking the industry’s highest-ever first quarter sales.

Qualcomm elected Harish Manwani to board of directors. Manwani brings more than 35 years of consumer product and global management experience, and currently serves as the Chief Operating Officer at Unilever PLC.

Blog review March 24, 2014

Monday, March 24th, 2014

IBS has recently issued a new white paper entitled Why Migration to 20nm Bulk CMOS and 16/14nm FinFETs Is Not the Best Approach for the Semiconductor Industry. Handel Jones of IBM says the focus of the analysis is on technology options that can be used to give lower cost per gate and lower cost per transistor within the next 24 to 60 months, covering the 28nm, 20nm and 14/16nm nodes.

Sitaram Arkalgud of Invensas and Rich Rogoff of Rudolph Technologies will present this Thursday as part of a free webcast focused on 2.5/3D integration and advanced packaging, including and new lithography options. Sitaram, who formerly led the 3D charge at SEMATECH, is now the vp of 3D technology at Invensas and Rich is the vp and general manager of the lithography systems group at Rudolph.

Phil Garrou provides a delightful lecture to the packaging community on nomenclature. He says the word “lecture” is one of those wonderful English words with multiple meanings. Lecture can mean “a talk or speech given to a group of people to teach them about a particular subject,” but it can also mean “a talk that criticizes someone’s behavior in an angry or serious way.” In his latest blog, lecturing means both!