Posts Tagged ‘3D IC’
By Ed Korczynski, Sr. Technical Editor, SST/SemiMD
Through-Silicon Vias (TSV) have finally reached mainstream commercial use for 3D ICs, though still for “high-end” high-performance applications. Despite allowing for extreme miniaturization, the demand for TSV has little to do with package size as evidenced by recent Samsung and TSMC product announcements for “enterprise servers” and “routers and other networking equipment.”
Used to connect opposite sides of a silicon substrate to allow for stacking of multiple Integrated Circuit (IC) chips in a single functional package, the industry has been using TSV in Micro-Electro-Mechanical Systems (MEMS) and Backside Image Sensors (BSI) manufacturing for many years now. Also, the first announcement of a commercial FPGA product using TSV in a so-called “2.5D” interposer package happened four years ago.
However, the Figure above shows that CIS and MEMS and 2.5D-FPGAs can all be categorized as “niche” applications with limited growth potentials. Specialty memory and logic (and eventually photonics) applications have long been seen as the major drivers of future TSV demand.
On September 25 of this year, TSMC announced it has collaborated with HiSilicon Technologies Co, Ltd. to create an ARM-based networking processor that integrates a 16nm-node logic chips with a 28nm-node I/O chip using silicon interposer technology. This is the same 2.5D TSMC-branded Chip-on-Wafer-on-Substrate (CoWoS) technology used in the Xilinx FPGA product. “This networking processor’s performance increases by three fold compared with its previous generation,” said HiSilicon President Teresa He. Package size reduction has nothing to do with the value of the products now demanding TSV.
Samsung announced last August that it has started mass producing the industry’s first 64GB DDR4 registered dual Inline memory modules (RDIMMs) using TSV. Targeting enterprise servers and “cloud” data centers, the new RDIMMs include 36 DDR4 packages, each of which consists of four 4-gigabit (Gb) DDR4 DRAM dice. The low-power chips are manufactured using Samsung’s 20nm-node process. The company claims that the new 64GB TSV module performs twice as fast as a 64GB module that uses wire-bonding, while consuming about half the power. Samsung has invested in TSV R&D since 2010 for 40nm-node 8GB DRAM RDIMMs and 2011 for 30nm-node 32GB DRAM RDIMMs.
The Hybrid Memory Cube (HMC) and other heterogeneous 3D-IC stacks based on TSV should be seen as long-term strategic technologies. HMC R&D led by Micron continues to serve near-term customers demanding ultra-high performance such as supercomputers and performance networking, as detailed in an SST article from last year. Micron’s Scott Graham, General Manager, Hybrid Memory Cube, commented then, “As we move forward in time, we’ll see technology evolve as costs come down for TSVs and manufacturing technology, it will enter into future space where traditional DDR type of memory has resided. Beyond DDR4, we can certainly see this technology being for mainstream memory.”
Elusive Demand for Mobile Applications
14 years ago, this editor—while working for an early innovator in TSV technology—was co-author of a “3D stacked wafer-level packaging” feature article in SST.
The lead paragraph of that article summarizes the advantages of using TSV to reduce package sizes:
As electronics applications shrink in size, integrated circuit (IC) packaged devices must be reduced both in footprint and in thickness. The main motivation for the development of smaller packages is the demand for portable communications devices, such as memory cards, smart cards, cellular telephones, and portable computing and gaming devices. End-users of such electronic devices are interested in greater functionality per unit volume, not relatively simplistic metrics, such as transistors per chip or circuit speed.
While still true, established and inherently lower-cost packaging technologies have been extended to allow for stacking of thinned silicon chips: wire-bonding can connect dozens of layers to a substrate, flip-chip with wire-bonding and substrate-vias can connect 4 layers easily, and both fan-in and fan-out packages can provide ample electrical Input/Output (I/O) connections. At SEMICON West this year in the annual Yield Forum breakfast sponsored by Entegris, Qualcomm vice president Dr. Geoffry Yu reminded attendees that, “TSV eventually will come, but the million dollar question is when. The market forces will dictate the answer.” What has become clear in the last year is that market demand for improved product performance will set the pace.
Matthew Hogan, a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, blogs that SoC Reliability Verification Doesn’t Just Happen, You Know. He says the best way to verify multi-IP, multiple power domain SoCs, is with the Unified Power Format (UPF), which enables a repeatable, comprehensive, and efficient design verification methodology, using industry standards, at the transistor level.
Dick James, Senior Technology Analyst, Chipworks, has a TSMC-fabbed 20-nm part in-house, and is looking forward to the analysis results. Wondering what changes TSMC has made from the 28-nm process, Dick says he expects mostly a shrink of the latter process, with no change to the materials of the high-k stack, though maybe to the sequence.
Ed Korczynski continues his theme of “Moore’s Law is Dead” with a third installment that looks at when that might happen. He says that at ~4nm pitch we run out of room “at the bottom,” after patterning costs explode at 45nm pitch.
Vivek Bakshi, EUV Litho, Inc. blogs about The 2014 EUVL Workshop which was held late last month amid some positive highlights and lots of R&D updates. The keynote talks this year were from Intel, Gigaphoton and Toshiba.
In his 201st Insights from The Leading Edge (IFTLE) blog post, Phil Garrou takes a look at some of the presentations at this year’s ConFab. Subramani Kengeri, Vice President, Advanced Technology Architecture for GlobalFoundries discussed the techno-economics of the semiconductor industry. Gary Patton, VP of IBM Semiconductor Research & Development Center addressed “Semiconductor Technology: Trends, Challenges, & Opportunities.” Adrian Maynes, 450C program manager, discussed the “450mm Transition Toward Sustainability: Facility & Infrastructure Requirements.”
Zvi Or-Bach, President and CEO of MonolithIC 3D Inc., blogs that over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.
An upcoming webcast will focus on The Rise of MEMS Sensors. Jay Esfandyari from STMicroelectronics will talk about how the introduction of MEMS technology into consumer markets has opened the floodgates with multiple MEMS – accelerometers, gyros, compasses, pressure sensors and microphones – in games such as the Wii and now in smartphones and tablets. Simone Severi from imec will Next, Simone Severi, lead for SiGe MEMS at imec, will discuss SiGe MEMS technology for monolithic integration on CMOS.
The Synopsys’ Galaxy Design Platform has been extended to support the Samsung-STMicroelectronics strategic agreement on 28nm FD-SOI. Adele Hars blogs that they’ve covered all the bases, so that designers going to Samsung’s foundry services for ST’s 28nm FD-SOI can hit the ground running.
Phil Garrou reports on the 16th biennial Symposium on Polymers, which was held this May in Wilmington DE. In this blog post, he analyzes presentations from Fraunhofer IZM, ASE and Hitachi Chemicals.
Jamie Girard, senior director, Public Policy, SEMI North America, blogs that with changes coming in Washington, SEMI has important work ahead supporting the innovators and job creators of this country. Advancing the goals of its members, SEMI advocates legislation in congress, targeting passage of the Commerce, Justice and Science Appropriations Act, increases to NSF and NIST funding and changes to R&D tax credits.
Zvi Or-Bach, President and CEO of MonolithIC 3D Inc. blogs that over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.
Prakash Arunkundrum, PwC Strategy and Operations Consulting Director blogs about improving financial predictability. He notes that there is continued evidence that despite spending several millions on IT transformations, improving internal planning processes, maturing supply chains, and streamlining product development processes, several companies still struggle with predicting their financial and operational performance.
The increased performance and the rapid shift from traditional handsets to consumer computing device post a number of manufacturing and supply chain challenges for fabless chip makers. Dr. Roawen Chen of Qualcomm says the scale of the challenges also creates an “extreme stress” for the existing foundry/fabless model to defend its excellence in this dynamic landscape. In a keynote talk at The ConFab, titled “what’s on our mind?” Dr. Chen will deliberate on a number of headwinds and opportunities.
Jean-Eric Michallet, Hughes Metras and Perrine Batude of CEA-Leti describe how the research group has already demonstrated the successful stacking of Si CMOS on Si CMOS, achieving benchmark performance for both layers of transistors. The main process challenge is to develop a sufficiently low-temperature process for the top transistor layer to limit the impact on the lower transistor layers.
Phil Garrou continues his analysis of the IMAPS Device Packaging Conference with a review of the keynote by AMD’s Bryan Black, titled“Die Stacking and High Bandwidth Memory.” Black stated that “…while die stacking is catching on in FPGAs, Power Devices, and MEMs, there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!” Garrou also reviews the newly announced STATSChipPAC FlexLine, which uses eWLB technology to dice and reconstitute incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size.
Karen Savala, president, SEMI Americas, blogs about the sustainable manufacturing imperative, noting that sustainability is increasingly considered a differentiating factor in global competitiveness relative to the technologies and products being provided. In conjunction with SEMICON West and INTERSOLAR North America, SEMI is organizing a four-day Sustainable Manufacturing Forum to share information about the latest technologies, products, and management approaches that promote sustainable manufacturing.
Pete Singer reports on what Handel Jones, founder and CEO of International Business Strategies (IBS), presented at SEMI’s Industry Strategy Symposium. Handel focused on key trends, factors impacting the growth of the industry and the migration to smaller feature dimensions. He is bullish about 2014 and industry innovation, but cautious about how quickly the industry will move to new technology nodes due to higher costs, and long design cycles.
Zvi Or-Bach, President and CEO of MonolithIC 3D believes that looking at the semi-equipment booking should be the first step in any attempt to assess future semiconductor trends. He writes that a new SEMI report seems to tell us that we are facing a new reality in the semiconductor industry: a Paradigm Shift.
Phil Garrou sorts out the difference between monolithic 3DICs and back end 3D with TSVs. He writes that back end (BE) 3DIC with TSV is a parallel process where each layer or stratum is fabricated with TSV separately and subsequently joined. Monolithic 3DIC is a front end (FE), sequential process where a second layer of silicon is deposited or grown onto the first finished chip and the transistor and interconnect processes are repeated.
A new type of transistor that could make possible fast and low-power computing devices for energy-constrained applications such as smart sensor networks, implantable medical electronics and ultra-mobile computing is feasible, according to Penn State researchers. Called a near broken-gap tunnel field effect transistor (TFET), the new device uses the quantum mechanical tunneling of electrons through an ultrathin energy barrier to provide high current at low voltage. Penn State, the National Institute of Standards and Technology and IQE, a specialty wafer manufacturer, jointly presented their findings at the International Electron Devices Meeting in Washington, D.C. The IEDM meeting includes representatives from all of the major chip companies and is the recognized forum for reporting breakthroughs in semiconductor and electronic technologies.
Based on a honeycomb network of carbon atoms, graphene could generate a type of electronic surface wave that would allow antennas just one micron long and 10 to 100nm wide to do the work of much larger antennas. While operating graphene nano-antennas have yet to be demonstrated, the researchers say their modeling and simulations show that nano-networks using the new approach are feasible with the alternative material.“We are exploiting the peculiar propagation of electrons in graphene to make a very small antenna that can radiate at much lower frequencies than classical metallic antennas of the same size,” said Ian Akyildiz, a Ken Byers Chair professor in Telecommunications in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. “We believe that this is just the beginning of a new networking and communications paradigm based on the use of graphene.”
This week, industry leaders and experts have gathered in Washington D.C. at the 59th annual IEEE International Electron Device Meeting (IEDM) conference. The IEDM presents more leading work in more areas of the field than any other technical conference, encompassing silicon and non-silicon device technology, molecular electronics, nanotechnology, optoelectronics, MEM/NEMS, energy-related devices and bioelectronics. The 59th annual IEDM conference includes a strong overall emphasis on circuit-device interaction, advanced semiconductor manufacturing, and biomedical devices. Solid State Technology‘s Pete Singer is on site all week, and we will be getting insight from bloggers and industry partners. Browse our slideshow of highlights from abstracts being presented this week.
The penetration of gallium nitride-on-silicon (GaN-on-Si) wafers into the light-emitting diode (LED) market is forecast to increase at a compound annual growth rate (CAGR) of 69 percent from 2013 to 2020, by which time they will account for 40 percent of all GaN LEDs manufactured, according to a new report from IHS Inc. In 2013, 95 percent of GaN LEDs will be manufactured on sapphire wafers, while only 1 percent will be manufactured on silicon wafers. The growth in the manufacturing of GaN-on-Si LEDs between 2013 and 2020 will take market share from both sapphire and silicon carbide wafers.
Soitec announced this week that the European Commission has approved the financing for the Guépard program, coordinated by Soitec. This program was launched to develop a new generation of highly efficient photovoltaic cells. It was selected in April 2012 by the “Invest for the Future” (Investissements d’Avenir) program, which is managed by the French environment and energy management agency (ADEME – Agence de l’Environnement et de la Maîtrise de l’Energie). As well as Soitec, Guépard brings together the French Alternative Energies and Atomic Energy Commission (CEA), and an SME, InPACT. For all these partners together it represents total investment of €68.9 million over five years. The European Commission’s notification to the French government of its funding approval will give Soitec access to €21.3 million in government support.
Invensas Corporation announced that it is partnering with Tezzaron Semiconductor Corp. a pioneer and producer of 3D Integrated Circuit (3D-IC) semiconductor devices, in order to build a wide range of 3D-IC customer products. Robert Patti, CTO of Tezzaron said: “We can produce complete high-quality 2.5D and 3D silicon devices, but the final packaging flows are lacking. Invensas’ 3D-IC packaging expertise and existing pilot assembly line capability will enable us to ramp our unique products into full production. The Invensas combination of technology development and low volume manufacturing capabilities are unlike anything else available.”
Phil Garrou completes his look at various packaging and 3D integration happenings from Semicon Taiwan, including news from Disco, Namics and Amkor. Choon Lee of Amkor, for example, predicted a silicon interposer cost of 2.7-4$/cm sq (100 sq mm) and expectations of organic interposer costs at 50% cost reduction.
Dynamic resource allocation can significantly improve turnaround time in post-tapeout flow. Mark Simmons of Mentor Graphics blogs about recent work that demonstrated 30% aggregate turnaround time improvement for a large set of jobs in conjunction with a greater than 90% average utilization across all hardware resources.
The MEMS Industry Group blog reflects on the trend toward sensor fusion and the role that hardware approaches such as FPGAs and microcontrollers will play in moving the technology forward.
44 years ago, the internet was born when two computers, one at UCLA and one at the Stanford Research Institute, connected over ARPANET (Advanced Research Projects Agency Network) to exchange the world’s first “host-to-host” message. Ricky Gradwohl of Applied Materials celebrates the “birthday” with thoughts on how far the internet has come.
Semiconductor Research Corporation launched the Semiconductor Synthetic Biology (SSB) research program on hybrid bio-semiconductor systems to provide insights and opportunities for future information and communication technologies. The program will initially fund research at six universities: MIT, the University of Massachusetts at Amherst, Yale, Georgia Tech, Brigham Young and the University of Washington. Approximately $2.25M will be invested by SRC-GRC for Phase 1 research.
North America-based manufacturers of semiconductor equipment posted $975.3 million in orders worldwide in September 2013 (three-month average basis) and a book-to-bill ratio of 0.97, according to the September EMDS Book-to-Bill Report published today by SEMI. A book-to-bill of 0.97 means that $97 worth of orders were received for every $100 of product billed for the month. The three-month average of worldwide bookings in September 2013 was $975.3 million. The bookings figure is 8.3 percent lower than the final August 2013 level of $1.06 billion, and is 6.8 percent higher than the September 2012 order level of $912.8 million. The three-month average of worldwide billings in September 2013 was $1.01 billion. The billings figure is 7.1 percent lower than the final August 2013 level of $1.08 billion, and is 13.6 percent lower than the September 2012 billings level of $1.16 billion.
Mentor Graphics Corporation announced its new Mentor Embedded Hypervisor product for in-vehicle infotainment (IVI) systems, telematics, advanced driver assistance systems (ADAS) and instrumentation. The Mentor Embedded Hypervisor is a small footprint Type 1 hypervisor developed specifically for embedded applications and intelligent connected devices. With the Mentor Embedded Hypervisor, developers can create high-performance systems that integrate and consolidate applications on multicore processors and make use of the ARM TrustZone. Development of new systems can be accelerated by reusing existing proprietary software and protecting intellectual property while incorporating Linux to leverage the open source ecosystem.
Cadence Design Systems, Inc. announced results for the third quarter of fiscal year 2013. Cadence reported third quarter 2013 revenue of $367 million, compared to revenue of $339 million reported for the same period in 2012. On a GAAP basis, Cadence recognized net income of $39 million, or $0.13 per share on a diluted basis, in the third quarter of 2013, compared to net income of $59 million, or $0.21 per share on a diluted basis, in the same period in 2012.
Researchers and physicians at Johns Hopkins University will collaborate with the nanoelectronics R&D center imec to advance silicon applications in healthcare, beginning with development of a device to enable a broad range of clinical tests. Imec and Johns Hopkins University hope to develop the next generation of “lab on a chip” concepts based on imec technology. The idea is that such a disposable chip could be loaded with a sample of blood, saliva or urine and then quickly analyzed using a smartphone, tablet or computer, making diagnostic testing faster and easier for applications such as disease monitoring and management, disease surveillance, rural health care and clinical trials.
A new Department of Energy grant will fund research to advance an additive manufacturing technique for fabricating three-dimensional (3D) nanoscale structures from a variety of materials. Using high-speed, thermally-energized jets to deliver both precursor materials and inert gas, the research will focus on dramatically accelerating growth, improving the purity and increasing the aspect ratio of the 3D structures. Known as focused electron beam induced deposition (FEBID), the technique delivers a tightly-focused beam of high energy electrons and an energetic jet of thermally excited precursor gases – both confined to the same spot on a substrate. Secondary electrons generated when the electron beam strikes the substrate cause decomposition of the precursor molecules, forming nanoscale 3D structures whose size, shape and location can be precisely controlled. This gas-jet assisted FEBID technique allows fabrication of high-purity nanoscale structures using a wide range of materials and combination of materials.
Despite a drop in global television unit demand in 2013, the semiconductor market for TVs is forecast to increase by an estimated seven percent to $13.1 billion, according to data presented in IC Insights’ upcoming IC Market Drivers 2014 report. Technologies such as wireless video connections, networking interfaces, multi-format decoders and LED backlighting have boosted the average semiconductor content in TV sets even as global TV unit shipments are forecast to decline by an estimated three percent in 2013, according to the report. IC Insights projects that total global semiconductor revenue for televisions will grow 12 percent to $14.7 billion in 2014 due to an uptick in new TV sales in advance of the 2014 Winter Olympic Games and the 2014 FIFA World Cup. Between 2012 and 2017, the semiconductor market for DTVs is forecast to grow at a healthy pace of 10 percent percent annually, increasing to $19.8 billion at the end of the forecast period.
CEA-Leti, Fraunhofer IPMS-CNT and three European companies — IPDiA, Picosun and SENTECH Instruments — have launched a project to industrialize 3D integrated capacitors with world-record density. The two-year, EC-funded PICS project is designed to develop a disruptive technology through the development of innovative ALD materials and tools that results in a new world record for integrated capacitor densities (over 500nF/mm2) combined with higher breakdown voltages. It will strengthen the SME partners’ position in several markets, such as automotive, medical and lighting, by offering an even higher integration level and more miniaturization.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.