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Posts Tagged ‘3D ASIP’

Packaging Conference Addresses Challenges, Opportunities in New Technologies

Friday, December 18th, 2015

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By Jeff Dorsch, Contributing Editor

On the second day of the 12th annual 3D ASIP conference, the heavy hitters came out to talk. Attendees heard presentations from executives of Amkor Technology, the Defense Advanced Research Projects Agency (DARPA), Northrop Grumman, Taiwan Semiconductor Manufacturing, Teledyne Scientific & Imaging, and Xilinx, among other companies.

The day began with Pioneer Awards presented to Mitsumasa Koyanagi of Tohoku University and Peter Ramm of Fraunhofer EMFT. Those two men then gave talks on their involvement in 3D packaging technology over the decades.

“It started with DRAM in 1974,” Koyanagi recalled.

Ramm reviewed various European initiatives in the field, including the development of InterChip Vias (ICVs), a precursor to through-silicon via (TSV) technology, and the concept of known good die.

Suresh Ramalingam of Xilinx discussed the attributes of Silicon-less Interconnect Technology (SLIT), which the chip company developed in cooperation with Siliconware Precision Industries (SPIL), the IC assembly, bumping, and testing contractor.

“It’s still a silicon platform,” he pointed out. SLIT promises to connect multiple die in a package without resorting to TSVs. “Wafer warpage is a big issue,” Ramalingam noted.

Amkor’s Mike Kelly followed Ramalingam. “There’s a kind of upturn or resurgence in 2.5D, driven by high-bandwidth memory,” he said.

Amkor is offering the Silicon-less Interposer Module (SLIM) as its TSV alternative technology, according to Kelly, while also providing Silicon Wafer Integrated Fan-out Technology (SWIFT) as another packaging alternative to TSV-based interconnections.

KC Yee of TSMC, filling in for an absent presenter, spoke at length about the foundry’s Integrated Fan-Out (InFO) wafer-level packaging technology. “InFO eliminates silicon, TSVs, interposers,” he said. At the same time, InFO “reduces cost,” he asserted.

DARPA’s Daniel Green spoke about the agency’s Diverse Accessible Heterogeneous Integration (DAHI) program, which succeeded its Compound Semiconductor Materials on Silicon (COSMOS) program.

He was followed by Augusto Gutierrez-Aitken of Northrop Grumman Aerospace Systems. “DAHI is not in competition with CMOS,” he said. NGAS is developing a foundry for heterogeneous integration projects, inviting in companies and universities to participate in the research and development.

Teledyne Scientific’s Miguel Urteaga spoke about his company’s CS-STACK 3D stacking chip program. “We’re looking to get the highest III-V performance we can,” he said.

Conference Features “The Year of Stacked Memory” in 2015

Thursday, December 17th, 2015

By Jeff Dorsch, Contributing Editor

The theme of this year’s 3D Architectures for Semiconductor Integration and Packading (3D ASIP) conference is “The Year of Stacked Memory,” noting how memory die stacked in one package are becoming more commonplace in 2015.

Put on by RTI International, the 3D ASIP conference is in its 12th year. Attendees and presenters are generally people involved in chip packaging, from academia and industry.

One presentation on Wednesday (December 16) was by Teruo Hirayama of Sony, which has a long history of developing CMOS image sensors, dating back to 1998 with the graphics synthesizer for the PlayStation 2 video-game console, employing embedded DRAMs.

Embedded DRAMs present a number of manufacturing challenges, such as requiring four photomasks at the time, compared with three masks for commodity DRAMs and two or so masks for “pure logic” chips, Hirayama noted.

To address the issue, Sony turned to “chip-on-chip” technology, combining the merits of system-on-a-chip devices and system-in-package technology, according to Hirayama. The chipmaker later resorted to stacked CMOS image sensors, which offer a cost advantage over conventional CMOS image sensors.

During fiscal 2014, stacked CMOS image sensors accounted for 64 percent of Sony’s CMOS image sensor shipments, with back-illuminated image sensors representing 31 percent and front-illuminated image sensors 5 percent, Hirayama reported.

For future directions in stacked image sensors, Hirayama pointed to connecting pixels to analog-to-digital converters, with a device that has memory, a microelectromechanical system device, and a radio-frequency chip on the bottom layer, topped with a logic device, the ADC, and pixels, in that order.

The conference also heard Wednesday from Bryan Black of Advanced Micro Devices, a senior AMD fellow who spearheaded development of the company’s Fiji graphics processing unit.

The project started in 2007 and took 8.5 years to complete, Black said. “The industry needed a new memory system,” he commented. “We ended up with a die-stacking solution.”

Virtual prototyping was employed along the way, according to Black.

With a silicon interposer measuring 1,011 square millimeters and an ASIC coming in at 592 square millimeters, with four high-bandwidth memories, the Fiji GPU module is a big device. “We realized the part was going to be much bigger than we expected,” Black recalled. “Then we realized this thing would be huge.”

Wrapping up on Wednesday, the conference also heard presentations by three suppliers of semiconductor production equipment – EV GroupSPTS Technologies, and Rudolph Technologies.

Time to “shift left” in chip design and verification, Synopsys founder says

Wednesday, March 4th, 2015

By Jeff Dorsch, contributing editor

The world is moving toward “Smart Everything,” according to Aart de Geus, founder, chairman, and co-CEO of Synopsys. “The door will open gradually, and then quickly,” he said in Tuesday’s keynote address at the Design and Verification Conference and Exhibition, or DVCon, in San Jose, Calif.

“The assisted brain is on the way,” de Geus told the standing-room-only audience. “This may be dreaming, but I don’t think so.”

Taking “Smart Design from Silicon to Software” as his official theme, the veteran executive urged attendees to “shift left” – in other words, “squeezing the schedule” to design, verify, debug, and manufacture semiconductors. “Schedules haven’t changed much,” de Geus said. The difference now is that the marketing department has as much influence in planning and scheduling a new product as the engineering department, he noted.

Chip designers also should “shift left” on semiconductor intellectual property, de Geus said. “IP reuse is the biggest change in 15 to 30 years,” he asserted. “Reuse leverages your innovation.”

After plugging the concepts of unified compilation and unified debugging architectures, de Geus touted the use of virtual prototypes in chip design. “Software guys are impatient with you,” he said. Synopsys, he noted, has created 400 million lines of software code.

Turning to the Internet of Things, de Geus said, “There are a lot of opportunities there.” The problem is “these things are full of cracks,” he added. There are significant engineering and security issues that must be addressed in networks of connected devices.

Developing the FinFET “was said to be impossible seven to eight years ago,” de Geus said. Nonetheless, the semiconductor industry was able to realize that advanced technology to move beyond the 28-nanometer process node, he noted. The future is likely to present similar challenges.

3D ASIP: “It’s Complicated”

Monday, December 15th, 2014

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By Jeff Dorsch, Contributing Editor

The presentations at this week’s 3D Architectures in Semiconductor Integration and Packaging conference could be summed up in a famous Facebook status: “It’s complicated.”

They also could be summed up in one word: Progress.

This year has seen tremendous progress in implementation of 3DIC technology, according to speakers at the 11th annual conference, held in Burlingame, Calif. Those who have been touting and tracking 3D chips for years are looking forward to the 2015 introduction of Intel’s Xeon Phi “Knights Landing” processor for high-performance computing, which will incorporate the Hybrid Memory Cube technology in the same package as the CPU.

Activities began Wednesday, December 10, with a preconference symposium on “2.5/3D-IC Design Tools and Flows” and “3D Integration: 3D Process Technology.” Bill Martin of E-System Design kicked off the program with a presentation on path finding, a topic addressed several times over the next two days. He emphasized that preparing for a chip design project, such as choosing the right tools, is as important as the design and implementation phases when it comes to embracing 3DIC technology.

John Ferguson of Mentor Graphics later said there is “an infrastructure problem” in the semiconductor industry when it comes to process design kits (PDKs) for 2.5D and 3D chips. Taiwan Semiconductor Manufacturing has collaborated with Mentor and other leading suppliers of electronic design automation tools to offer PDKs to TSMC foundry customers, yet the next step must be taken to have outsourced semiconductor assembly and test contractors provide packaging PDKs.

Phil Garrou, a senior consultant for Yole Developpement, said 2014 has witnessed significant progress in implementation of 3DIC technology. “We no longer need to prove performance,” he said. “The remaining issue is cost.”

Several speakers addressed the topic of the Internet of Things and how it involves 3DICs on the first day of the conference. Steven Schulz of the Silicon Integration Initiative (Si2) said 3D chip designers should think of their products not as system-on-a-chip devices, but system-on-a-stack.

Yole’s Rozalia Beica said predictions that the Internet of Things market will be worth trillions of dollars in 2022 are “overoptimistic” and that “optimism is higher than current investment.” Yole looks for the market in IoT sensors to be worth $400 billion in 2024, she said.

Samta Bonsal of the GE Software Center spoke on the Industrial Internet. “That world is huge,” she said, and predicted it will have “a bigger impact” than consumer-oriented IoT applications. Gartner says the market for all IoT chips will be worth $7.58 billion in 2015, she noted. The market research firm also forecasts that 8 billion connected devices will be shipped during 2020, encompassing 35 billion semiconductor devices produced on 6 million wafers.

E. Jan Vardaman of TechSearch International presented a lively review of 3DIC technology, past and present. “There’s been a lot of good progress with TSV (through-silicon vias), enabling us to improve the process,” she said. Still, 3DIC has been a long time in coming, noting that Micron Technology began research and development on DRAM stacking a dozen years ago and Xilinx initiated development of a silicon-based interposer to be used with TSVs in 2006, six years before it was able to offer a field-programmable gate array with such technology, manufactured in volume by TSMC.

Dyi-Chung Hu of Unimicron looked past the silicon interposer to the era to using glass for interposers and substrate core materials. Glass has a low coefficient of thermal expansion compared with silicon, he noted, and is very flat. Its chief drawback is its brittleness, according to Hu.

Michael Gaynes of IBM’s Thomas J. Watson Research Center reported on his company’s two ICECool projects for the Defense Advanced Research Projects Agency, developing 3DICs that could run cooler in data-center servers.

The last day of the conference coincided with a convention devoted to the Star Trek television series in the adjacent hotel ballroom. Attendees dressed as Klingons and starship crew members mingled with the 3DIC technologists in the hotel lobby, all dreaming and thinking about the future.