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Posts Tagged ‘300mm’

Applied Materials’ Olympia ALD Spins Powerful New Capabilities

Monday, July 13th, 2015

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By Ed Korczynski, Sr. Technical Editor

Applied Materials today unveiled the Applied Olympia ALD system, using thermal sequential-ALD technology for the high-volume manufacturing (HVM) of leading-edge 3D memory and logic chips. Strictly speaking this is a mini-batch tool, since four 300mm wafers are loaded onto a turn-table in the chamber that continuously rotates through four gas-isolated modular processing zones. Each zone can be configured to flow any arbitrary ALD precursor or to exposure the surface to Rapid-Thermal-Processing (RTP) illumination, so an extraordinary combination of ALD processes can be run in the tool. “What are the applications that will result from this? We don’t know yet because the world has never before had a tool which could provide these capabilities,” said David Chu, Strategic Marketing, Applied’s Dielectric Systems and Modules group.

Fig.1: The four zones within the Olympia sequential-ALD chamber can be configured to use any combination of precursors or treatments. (Source: Applied Materials)

Figure 1 shows that in addition to a high-throughput simple ALD process such that wafers would rotate through A-B-A-B precursors in sequence, or zones configured in an A-B-C-B sequence to produce a nano-laminate such as Zirconia-Alumina-Zirconia (ZAZ), almost any combination of pre- and post-treatments can be used. The gas-panel and chemical source sub-systems in the tool allow for the use up to 4 precursors. Consequently, Olympia opens the way to depositing the widest spectrum of next-generation atomic-scale conformal films including advanced patterning films, higher- and lower-k dielectrics, low-temperature films, and nano-laminates.

“The Olympia system overcomes fundamental limitations chipmakers are experiencing with conventional ALD technologies, such as reduced chemistry control of single-wafer solutions and long cycle times of furnaces,” Dr. Mukund Srinivasan, vice president and general manager of Applied’s Dielectric Systems and Modules group. “Because of this, we’re seeing strong market response, with Olympia systems installed at multiple customers to support their move to 10nm and beyond.” Future device structures will need more and more conformal ALD, as new materials will have to coat new 3D features.

When engineering even-smaller structures using ALD, thermal budgets inherently decrease to prevent atomic inter-diffusion. Compared to thermal ALD, Plasma-Enhanced ALD (PEALD) functions at reduced temperatures but tend to induce impurities in the film because of excess energy in the chamber. The ability of Olympia to do RTP for each sequentially deposited atomic-layer leads to final film properties that are inherently superior in defectivity levels to PEALD films at the same thermal budget:  alumina, silica, silicon-nitride, titania, and titanium-nitride depositions into high aspect-ratio structures have been shown.

Purging (from the tool) pump-purge

Fab engineers who have to deal with ALD technology—from process to facilities—should be very happy working with Olympia because the precursors flow through the chamber continuously instead of having to use the pump-purge sequences typical of single-wafer and mini-batch ALD tools used for IC fabrication. Pump-purge sequences in ALD tools result in the following wastes:

*   Wasted chemistry since tools generally shunt precursor-A past the chamber directly to the pump-line when precursor-B is flowing and vice-versa,

*   More wasted chemistry because the entire chamber gets coated along with the wafer,

*   Wasted cleaning chemistry during routine chamber and pump preventative-maintenance,

*   Wasted downtime to clean the chamber and pump, and

*   Wasted device yield because precursors flowing in the same space at different times can accidentally overlap and create defects.

“Today there are chemistries that are more or less compatible with tools,” reminded Chu. “When you try to use less-compatible chemistries, the purge times in single-wafer tools really begin to reduce the productivity of the process. There are chemistries out there today that would be desirable to use that are not pursued due to the limitations of pump-purge chambers.”

—E.K.

Solid State Watch: October 31-November 6, 2014

Monday, November 10th, 2014
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The Week in Review: Nov. 22, 2013

Friday, November 22nd, 2013

GLOBALFOUNDRIES, Open-Silicon and Amkor Technology have jointly exhibited a functional system-on-chip (SoC) solution on a 2.5D silicon interposer featuring two 28nm logic chips, with embedded ARM processors. The jointly developed design is a test vehicle that showcases the benefits of 2.5D technology for mobile and low-power server applications. The companies recently demonstrated the functioning SoC at ARM TechCon in Santa Clara, CA.

North America-based manufacturers of semiconductor equipment posted $1.12 billion in orders worldwide in October 2013 (three-month average basis) and a book-to-bill ratio of 1.05, according to the October EMDS Book-to-Bill Report published this week by SEMI.   A book-to-bill of 1.05 means that $105 worth of orders were received for every $100 of product billed for the month. “Both equipment orders and billings improved in the October data, resulting in a book-to-bill ratio returning above parity,” said Denny McGuirk, president and CEO of SEMI.  ”Order activity is well above the figures reported one year ago and point towards on-going investments in advanced process technologies for NAND Flash, microprocessor, and foundry.”

Soraa, a developer of GaN on GaN LED technology, announced that it will open a new semiconductor fabrication plant in Buffalo, New York. In partnership with the State of New York, the company will construct a new state-of-the-art GaN on GaN LED fabrication facility that will employ hundreds of workers. The new facility is projected to be operational in 2015. Soraa currently operates an LED fabrication plant in Fremont, California, one of only a few in the US.

Dow Corning introduced new Dow Corning MS-2002 Moldable White Reflector Silicone at Strategies in Light Europe 2013. This highly reflective white material extends the excellent photo-thermal stability and high-moldability that typifies Dow Corning’s award-winning optical-grade Moldable Silicone family to the reflective elements of LED lamp and luminaire applications. Dow Corning MS-2002 Moldable White Reflector Silicone targets reflectivity as high as 98 percent to help further boost light output from LED devices, improve overall energy efficiency and prolong device reliability.

SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets, has successfully installed an ELP300 excimer laser stepper to support next generation advanced packaging and 3D IC laser debonding applications at the Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin. The ELP300 excimer laser platform is designed for high volume manufacturing and processing of 100mm to 300mm wafers.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, introduced the EVG PHABLE exposure system, which is designed specifically for manufacturing photonic components.  Leveraging EVG’s expertise in photolithography, the EVG PHABLE system incorporates a unique contactless lithography mask-based approach that enables full-field, high-resolution and cost-efficient micro- and nanopatterning of passive and active photonic components, such as patterned structures on light emitting diode (LED) wafers, in high-throughput production environments.

The Week In Review: Nov. 7, 2013

Friday, November 8th, 2013

Peregrine Semiconductor Corp. and GLOBALFOUNDRIES are sampling the first RF Switches built on Peregrine’s new UltraCMOS 10 RF SOI technologies. This partnership unites Peregrine’s 25 years of RF SOI experience with a tier-one foundry. In a joint development effort, GLOBALFOUNDRIES and Peregrine created a unique fabrication flow for the versatile, new, 130 nm UltraCMOS 10 technology platform. This new technology delivers a more than 50-percent performance improvement over comparable solutions. UltraCMOS 10 technology gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks.

Peregrine Semiconductor this week celebrated two significant milestones – its 25th anniversary of pioneering RF SOI solutions and the shipment of the two-billionth chip. Peregrine reaches the two-billionth-chip milestone in an order to Murata Manufacturing Company, the supplier of RF front-end modules for the global mobile wireless marketplace.

Rubicon Technology announced the launch of the first commercial line of large diameter patterned sapphire substrates (PSS) in four-inch through eight-inch diameters.  This new product line provides LED chip manufacturers with a ready-made source of large diameter PSS to serve the needs of the rapidly growing LED general lighting industry.

Semiconductor Research Corporation and Northeastern University researchers announced advancements in radio-frequency (RF) circuit technology that promise to improve and widen the applications of mobile devices.

Imec announced that it has successfully demonstrated the first III-V compound semiconductor FinFET devices integrated epitaxially on 300mm silicon wafers, through a unique silicon fin replacement process. The achievement illustrates progress toward 300mm and future 450mm high-volume wafer manufacturing of advanced heterogeneous CMOS devices, monolithically integrating high-density compound semiconductors on silicon.

STMicroelectronics announced this week its close collaboration with Memoir Systems has made the revolutionary Algorithmic Memory Technology available for embedded memories in application-specific integrated circuits (ASICs) and Systems on Chips (SoCs) manufactured in ST’s fully-depleted silicon-on-insulator (FD-SOI) process technology.

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Research News: Nov. 5, 2013

Tuesday, November 5th, 2013

Imec, a nanoelectronics research center, announced today that it has successfully demonstrated the first III-V compound semiconductor FinFET devices integrated epitaxially on 300mm silicon wafers, through a unique silicon fin replacement process. The achievement illustrates progress toward 300mm and future 450mm high-volume wafer manufacturing of advanced heterogeneous CMOS devices, monolithically integrating high-density compound semiconductors on silicon. The breakthrough not only enables continual CMOS scaling down to 7nm and below, but also enables new heterogeneous system opportunities in hybrid CMOS-RF and CMOS-optoelectronics. “To our knowledge, this is the world’s first functioning CMOS compatible IIIV FinFET device processed on 300mm wafers,” stated An Steegen, senior vice president core CMOS at imec. “This is an exciting accomplishment, demonstrating the technology as a viable next-generation alternative for the current state-of-the-art Si-based FinFET technology in high volume production.”

Columbia Engineering researchers have experimentally demonstrated for the first time that it is possible to electrically contact an atomically thin two-dimensional (2D) material only along its one-dimensional (1D) edge, rather than contacting it from the top, which has been the conventional approach. With this new contact architecture, they have developed a new assembly technique for layered materials that prevents contamination at the interfaces, and, using graphene as the model 2D material, show that these two methods in combination result in the cleanest graphene yet realized. The study is published in Science on November 1, 2013. The researchers fully encapsulated the 2D graphene layer in a sandwich of thin insulating boron nitride crystals, employing a new technique in which crystal layers are stacked one-by-one. Once they created the stack, they etched it to expose the edge of the graphene layer, and then evaporated metal onto the edge to create the electrical contact. By making contact along the edge, the team realized a 1D interface between the 2D active layer and 3D metal electrode. And, even though electrons entered only at the 1D atomic edge of the graphene sheet, the contact resistance was remarkably low, reaching 100 Ohms per micron of contact width—a value smaller than what can be achieved for contacts at the graphene top surface.

UPV/EHU-University of the Basque Country researchers have developed and patented a new source of light emitter based on boron nitride nanotubes and suitable for developing high-efficiency optoelectronic devices. Scientists are usually after defect-free nano-structures. Yet in this case the UPV/EHU researcher Angel Rubio and his collaborators have put the structural defects in boron nitride nanotubes to maximum use. The outcome of his research is a new light-emitting source that can easily be incorporated into current microelectronics technology. The research has also resulted in a patent.