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Posts Tagged ‘2D’

2D Materials May Be Brittle

Tuesday, November 15th, 2016

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By Ed Korczynski, Sr. Technical Editor

International researchers using a novel in situ quantitative tensile testing platform have tested the uniform in-plane loading of freestanding membranes of 2D materials inside a scanning electron microscope (SEM). Led by materials researchers at Rice University, the in situ tensile testing reveals the brittle fracture of large-area molybdenum diselenide (MoSe2) crystals and measures their fracture strength for the first time. Borophene monolayers with a wavy topography are more flexible.

A communication to Advanced Materials online (DOI: 10.1002/adma.201604201) titled “Brittle Fracture of 2D MoSe2” by Yinchao Yang et al. disclosed work by researchers from the USA and China led by Department of Materials Science and NanoEngineering Professor Jun Lou at Rice University, Houston, Texas. His team found that MoSe2 is more brittle than expected, and that flaws as small as one missing atom can initiate catastrophic cracking under strain.

“It turns out not all 2D crystals are equal. Graphene is a lot more robust compared with some of the others we’re dealing with right now, like this molybdenum diselenide,” says Lou. “We think it has something to do with defects inherent to these materials. It’s very hard to detect them. Even if a cluster of vacancies makes a bigger hole, it’s difficult to find using any technique.” The team has posted a short animation online showing crack propagation.

2D Materials in a 3D World -222

While all real physical things in our world are inherently built as three-dimensional (3D) structures, a single layer of flat atoms approximates a two-dimensional (2D) structure. Except for special superconducting crystals frozen below the Curie temperature, when electrons flow through 3D materials there are always collisions which increase resistance and heat. However, certain single layers of crystals have atoms aligned such that electron transport is essentially confined within the 2D plane, and those electrons may move “ballistically” without being slowed by collisions.

MoSe2 is a dichalcogenide, a 2D semiconducting material that appears as a graphene-like hexagonal array from above but is actually a sandwich of Mo atoms between two layers of Se chalcogen atoms. MoSe2 is being considered for use as transistors and in next-generation solar cells, photodetectors, and catalysts as well as electronic and optical devices.

The Figure shows the micron-scale sample holder inside a SEM, where natural van der Waals forces held the sample in place on springy cantilever arms that measured the applied stress. Lead-author Yang is a postdoctoral researcher at Rice who developed a new dry-transfer process to exfoliate MoSe2 from the surface upon which it had been grown by chemical vapor deposition (CVD).

Custom built micron-scale mechanical jig used to test mechanical properties of nano-scale materials. (Source: Lou Group/Rice University)

The team measured the elastic modulus—the amount of stretching a material can handle and still return to its initial state—of MoSe2 at 177.2 (plus or minus 9.3) gigapascals (GPa). Graphene is more than five times as elastic. The fracture strength—amount of stretching a material can handle before breaking—was measured at 4.8 (plus or minus 2.9) GPa. Graphene is nearly 25 times stronger.

“The important message of this work is the brittle nature of these materials,” Lou says. “A lot of people are thinking about using 2D crystals because they’re inherently thin. They’re thinking about flexible electronics because they are semiconductors and their theoretical elastic strength should be very high. According to our calculations, they can be stretched up to 10 percent. The samples we have tested so far broke at 2 to 3 percent (of the theoretical maximum) at most.”

Borophene

“Wavy” borophene might be better, according to finding of other Rice University scientists. The Rice lab of theoretical physicist Boris Yakobson and experimental collaborators observed examples of naturally undulating metallic borophene—an atom-thick layer of boron—and suggested that transferring it onto an elastic surface would preserve the material’s stretchability along with its useful electronic properties.

Highly conductive graphene has promise for flexible electronics, but it is too stiff for devices that must repeatably bend, stretch, compress, or even twist. The Rice researchers found that borophene deposited on a silver substrate develops nanoscale corrugations, and due to weak binding to the silver can be exfoliated for transfer to a flexible surface. The research appeared recently in the American Chemical Society journal Nano Letters.

Rice University has been one of the world’s leading locations for the exploration of 1D and 2D materials research, ever since it was lucky enough to get a visionary genius like Richard Smalley to show up in 1976, so we should expect excellent work from people in their department of Materials Science and NanoEngineering (CSNE). Still, this ground-breaking work is being done in labs using tools capable of handling micron-scale substrates, so even after a metaphorical “path” has been found it will take a lot of work to build up a manufacturing roadway capable of fabricating meter-scale substrates.

—E.K.

5nm Node Needs EUV for Economics

Thursday, January 29th, 2015

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By Ed Korczynski, Sr. Technical Editor

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At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.

Fig. 1: Panelists discuss future IC manufacturing and design possibilities in San Francisco on December 16, 2014. (Source: Pete Singer)

Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:

  • Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
  • Michael Guillorn, Ph.D. – research staff member, IBM,
  • Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
  • Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
  • Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.

Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.

Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.

Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm:  gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.

Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.

Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:

  1. everything is an interface requiring precision materials engineering,
  2. film depositions are either atomic-layer or selective films or even lattice-matched,
  3. pattern definition using dry selective-removal and directed self-assembly, and
  4. architecture in 3D means high aspect-ratio processing and non-equilibrium processing.

An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.

Fig. 2: ElectroMigration (EM) lifetimes for on-chip interconnects made with either conventional Cu or Cu lined and capped with Co, showing 10 times improvement with the latter. (Source: Applied Materials)

“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.

There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.

However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”

Research Alert: September 3, 2014

Wednesday, September 3rd, 2014

A new, tunable device for spintronics

Spin-charge converters are important devices in spintronics, an electronic which is not only based on the charge of electrons but also on their spin and the spin-related magnetism. Spin-charge converters enable the transformation of electric into magnetic signals and vice versa. Recently, the research group of Professor Jairo Sinova from the Institute of Physics at Johannes Gutenberg University Mainz in collaboration with researchers from the UK, Prague, and Japan, has for the first time realized a new, efficient spin-charge converter based on the common semiconductor material GaAs.

Comparable efficiencies had so far only been observed in platinum, a heavy metal. In addition, the physicists demonstrated that the creation or detection efficiency of spin currents is electrically tunable in a certain regime. This is important when it comes to real devices. The underlying mechanism, that was revealed by theoretical works of the Sinova group, opens up a new approach in searching and engineering spintronic materials. These results have recently been published in the journal Nature Materials.

Making use of electron spin for information transmission and storage, enables the development of electronic devices with new functionalities and higher efficiency. To make real use of the electron spin, it has to be manipulated precisely: it has to be aligned, transmitted and detected. The work of Sinova and his colleagues shows, that it is possible to do so using electric fields rather than magnetic ones. Thus, the very efficient, simple and precise mechanisms of charge manipulation well established in semiconductor electronics can be transferred to the world of spintronic and thereby combine semiconductor physics with magnetism.

Now, Sinova and his colleagues have shown that gallium-arsenide (GaAs), a very common and widely used semiconductor material, can be an as efficient spin-charge converter as platinum, even at room temperature, which is important for practical applications. Moreover, the physicists have demonstrated for the first time that the efficiency can be tuned continuously by varying the electric field that drives the electrons.

The reason for this – as theoretical calculations of the Sinova group have shown – lies in the existence of certain valleys in the conduction band of the semiconductor material. One can think of the conduction band and its valleys as of a motor highway with different lanes, each one requiring a certain minimum velocity. Applying a higher electric field enables a transition from one lane to the other.

Since the spin-orbit coupling is different in each lane, a transition also affects the strength of the spin-hall effect. By varying the electric field, the scientists can distribute the electron spins on the different lanes, thus varying the efficiency of their spin-charge converter.

By taking into account the valleys in the conduction band, Sinova and his colleagues open up new ways to find and engineer highly efficient materials for spintronics. Especially, since current semiconductor growth technologies are capable of engineering the energy levels of the valleys and the strength of spin-orbit coupling, e.g. by substituting Ga or As with other materials like Aluminum.

Copper shines as flexible conductor

By turning instead to copper, both abundant and cheap, researchers at Monash University and the Melbourne Centre for Nanofabrication have developed a way of making flexible conductors cost-effective enough for commercial application.

“Aerogel monoliths are like kitchen sponges but ours are made of ultra fine copper nanowires, using a fabrication process called freeze drying,” said lead researcher Associate Professor Wenlong Cheng, from Monash University’s Department of Chemical Engineering.

“The copper aerogel monoliths are conductive and could be further embedded into polymeric elastomers – extremely flexible, stretchable materials – to obtain conducting rubbers.”

Despite its conductivity, copper’s tendency to oxidation and the poor mechanical stability of copper nanowire aerogel monoliths mean its potential has been largely unexplored.

The researchers found that adding a trace amount of poly(vinyl alcohol) (PVA) to their aerogels substantially improved their mechanical strength and robustness without impairing their conductivity.

What’s more, once the PVA was included, the aerogels could be used to make electrically conductive rubber materials without the need for any prewiring. Reshaping was also easy.

“The conducting rubbers could be shaped in arbitrary 1D, 2D and 3D shapes simply by cutting, while maintaining the conductivities,” Associate Professor Cheng said.

The versatility extends to the degree of conductivity. “The conductivity can be tuned simply by adjusting the loading of copper nanowires,” he said. “A low loading of nano wires would be appropriate for a pressure sensor whereas a high loading is suitable for a stretchable conductor.”

Affordable versions of these materials open up the potential for use in a range of new-generation concepts: from prosthetic skin to electronic paper, for implantable medical devices, and for flexible displays and touch screens.

They can be used in rubber-like electronic devices that, unlike paper-like electronic devices, can stretch as well as bend. They can also be attached to topologically complex curved surfaces, serving as real skin-like sensing devices, Associate Professor Cheng said.

In their report, published recently in ACS Nano, the researchers noted that devices using their copper-based aerogels were not quite as sensitive as those using gold nanowires, but had many other advantages, most notably their low-cost materials, simpler and more affordable processing, and great versatility.

Competition for graphene

A new argument has just been added to the growing case for graphene being bumped off its pedestal as the next big thing in the high-tech world by the two-dimensional semiconductors known as MX2 materials. An international collaboration of researchers led by a scientist with the U.S. Department of Energy (DOE)’s Lawrence Berkeley National Laboratory (Berkeley Lab) has reported the first experimental observation of ultrafast charge transfer in photo-excited MX2 materials. The recorded charge transfer time clocked in at under 50 femtoseconds, comparable to the fastest times recorded for organic photovoltaics.

“We’ve demonstrated, for the first time, efficient charge transfer in MX2 heterostructures through combined photoluminescence mapping and transient absorption measurements,” says Feng Wang, a condensed matter physicist with Berkeley Lab’s Materials Sciences Division and the University of California (UC) Berkeley’s Physics Department. “Having quantitatively determined charge transfer time to be less than 50 femtoseconds, our study suggests that MX2 heterostructures, with their remarkable electrical and optical properties and the rapid development of large-area synthesis, hold great promise for future photonic and optoelectronic applications.”

Wang is the corresponding author of a paper in Nature Nanotechnology describing this research. The paper is titled “Ultrafast charge transfer in atomically thin MoS2/WS2 heterostructures.” Co-authors are Xiaoping Hong, Jonghwan Kim, Su-Fei Shi, Yu Zhang, Chenhao Jin, Yinghui Sun, Sefaattin Tongay, Junqiao Wu and Yanfeng Zhang.

MX2 monolayers consist of a single layer of transition metal atoms, such as molybdenum (Mo) or tungsten (W), sandwiched between two layers of chalcogen atoms, such as sulfur (S). The resulting heterostructure is bound by the relatively weak intermolecular attraction known as the van der Waals force. These 2D semiconductors feature the same hexagonal “honeycombed” structure as graphene and superfast electrical conductance, but, unlike graphene, they have natural energy band-gaps. This facilitates their application in transistors and other electronic devices because, unlike graphene, their electrical conductance can be switched off.

“Combining different MX2 layers together allows one to control their physical properties,” says Wang, who is also an investigator with the Kavli Energy NanoSciences Institute (Kavli-ENSI). “For example, the combination of MoS2 and WS2 forms a type-II semiconductor that enables fast charge separation. The separation of photoexcited electrons and holes is essential for driving an electrical current in a photodetector or solar cell.”

In demonstrating the ultrafast charge separation capabilities of atomically thin samples of MoS2/WS2 heterostructures, Wang and his collaborators have opened up potentially rich new avenues, not only for photonics and optoelectronics, but also for photovoltaics.

“MX2 semiconductors have extremely strong optical absorption properties and compared with organic photovoltaic materials, have a crystalline structure and better electrical transport properties,” Wang says. “Factor in a femtosecond charge transfer rate and MX2 semiconductors provide an ideal way to spatially separate electrons and holes for electrical collection and utilization.”

Wang and his colleagues are studying the microscopic origins of  charge transfer in MX2 heterostructures and the variation in charge transfer rates between different MX2 materials.

“We’re also interested in controlling the charge transfer process with external electrical fields as a means of utilizing MX2 heterostructures in photovoltaic devices,” Wang says.

This research was supported by an Early Career Research Award from the DOE Office of Science through UC Berkeley, and by funding agencies in China through the Peking University in Beijing.