By Jeff Chappell
There may have been a time when AMD founder Jerry Sanders famous quote: “real men (i.e., real companies) have their own fabs” rang true, but in today’s business climate it seems quaint at best.

Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues by offering foundry services—Intel and Samsung among them. Then there is the fact that the third-largest chipmaker in 2012, in terms of revenue, was a pure-play foundry.

As the 28nm node capacity ramp continues in the foundry market in 2013, following unexpected demand and capacity bottlenecks in 2012, today’s foundry market is the end result of market trends and forces with old roots. But those trends and forces have been compounded in modern times by extreme financial and market necessities, not to mention technology.

In one sense, however, at its core, the foundry market hasn’t changed since Taiwan Semiconductor Manufacturing Co. (TSMC) launched as the industry’s first pure-play foundry in 1987: Chip companies look to foundries, either as a customer or as a provider, to maximize productivity and thereby minimize costs. That part of the game hasn’t changed, whether it involves a component supplier designing power modules with 0.18-micron design rules for manufacturing on 200mm wafers, or one of the two GPU giants producing their next-generation graphics processors based on the latest technology.

The trend for years now has been fabless or fab-lite; even Sanders’ own AMD spun out its manufacturing arm several years ago to create one of the world’s largest pure-play foundries, GlobalFoundries. This has naturally in turn spawned the growth of the pure-play foundry market from its birth some 26 years ago.

Indeed, last year the overall foundry market enjoyed revenues of $29.6 billion, managing year-over-year growth of 12%, which is three times that of the chip industry over all in 2012. That growth caught everyone by surprise including the foundries themselves; 28nm capacity was tight for much of the year, even as yields improved dramatically—so much so that it reportedly impacted some capital equipment purchases, in spite of tight foundry capacity.

But that illustrates the biggest and most obvious change in the foundry industry in modern times: The foundries themselves are involved directly with developing leading-edge semiconductor technology. In fact, with the industry looking at the end of planar CMOS at the leading edge for some devices with the advent of 3D transistor architectures and the high-k materials they require, leading foundries no longer can rely on a mix of conventional scaling, publicly available data and equipment and process technology suppliers to get their jobs done. Research and development now must be within their purview, at least for those playing at the leading edge.

“Historically foundries don’t do R&D, their clients do it,” noted Dean Freeman, a research vice president at Gartner Research. That’s not so, today.

Nothing illustrates that fact better than TSMC’s R&D budget. In 2012 the company spent 33.8 billion NT, or about $1.13 billion, on R&D—a quarter of its revenue. This year the company plans to spend 40.4 billion NT, or about $1.35 billion, which includes adding some 500 people to its employee headcount, bolstering its R&D staff from 3,400 people to 3,900.

Indeed, leading foundries have joined the leading IDMs and technology consortia as purveyors of—not just manufacturers of—advanced technology.

While TSMC and its foundry brethren in the first tier of the pure-play market—Globalfoundries and United Microelectronics Corp. (UMC)—continue to build out 28nm capacity, they are also hard at work on the 20nm node and the subsequent hybrid 14/16nm finFET based on a 20nm back-end of line process. In fact, TSMC just announced first tapeouts of an ARM A-57 processor, based on the 64-bit ARMv8 processor series and built with 16nm transistor technology, including finFETs. This followed their rival’s announcement of a few months earlier. In February, GlobalFoundries announced a “first implementation” of a dual-core ARM A9 processor using the company’s 14nm-XM FinFET transistor architecture.

Follow the money
Being on the very leading edge of technology is driving growth among the first-tier foundries.

Like many others in the industry, TSMC and its chairman and CEO, Morris Chang, are quite bullish on the continued demand for 28nm technology as well as the development of 20nm technology. In general, 28nm designs, with their combination of lower power consumption and speedier transistors, have consequently proven cost-effective for a chip industry currently driven by mobile devices—smartphones, tablets and ultra lightweight notebooks. During TSMC’s review of its 2012 results earlier this year, Chang said the company will continue to aggressively grow its 28nm capacity and output; 2013 capacity and output will triple that of 2012, he said.

“It’s all about lower power with functionality and no sacrifice on the power requirements,” observed Kathryn Ta, managing director of strategic marketing for Applied Materials’ Silicon Systems Group. The equipment and process technology supplier’s foundry customers are seeing a need to move to 3D transistor architectures with minimal leakage, she said, because of those power requirements.

Development will continue at 20nm and 16nm as well at TSMC and its rivals. This year, 88% of the 9 billion NT that TSMC will spend on capital expenditures will go to 28nm, 20nm and 16nm capacity; an additional 5% will be spent on additional R&D equipment. Chang predicted that by Q3 of this year high-k metal gate production will surpass that of standard oxynitride gates, a gap that naturally will widen in Q4 and beyond.

“Enough discussions have taken place with enough customers … to lead us to believe that in both its first and second year of production (2014 and 2015, respectively) the volume of 20nm SoCs will be larger than that of 28nm in its first and second years of production (2012 and 2013),” Chang said.

He further noted that this represented the state of the art, and not just for the foundry industry, but for the industry as whole. This may indeed prove to be true in a few years as those 20nm and 16nm/14nm SoC devices move into production. It’s a far cry from the days when foundries were traditionally technological also-rans.

But then the first-tier foundries at the leading edge are still playing catch-up in the meantime with those IDMs at the leading edge, namely Intel. The world’s biggest chipmaker has kept Moore’s Law on track on the CPU side of the ITRS roadmap, last year having brought its Ivy Bridge processors to market. These feature 22nm transistors replete with finFETs; Intel’s own roadmap calls for 14nm designs to be in production in 2014; in terms of mobile SoCs like those the foundries are talking about, the company has promised its 22nm Atom SoCs will be in production in 2015.

“Intel seems to be able to continue to shrink because they spend a fortune on R&D,” said Gartner’s Freeman. “The foundries are pushing hard to catch up,” He noted that while both GlobalFoundries and TSMC have 16nm/14nm chips featuring finFETs in development, they are taking a shortcut, so to speak, by employing 20nm metal interconnects. “It’s close to what Intel is doing. Intel’s design may be more sophisticated, but the lithography is the same.”

Plenty of room, and business, at the trailing end
But not everybody in the foundry market is playing at the leading edge. The same market and industry forces that have induced the bigger pure-play foundries to move beyond their historical roles also have created a two-tiered pure-play foundry market. In the first tier are those that have the deep pockets to play in this space: TSMC, Globalfoundries, UMC, and to a lesser extent China’s Semiconductor Manufacturing International Corp. (SMIC).

Then there are the second-tier companies, those that are still fulfilling a traditional foundry role—at trailing edge processes, but nevertheless needed or even essential semiconductor manufacturing technology and capacity. Indeed, many second-tier foundries do quite well with their particular market niches and technologies. In the world of mobile consumer gadgets, including but not limited to smartphones and tablets, there are still many components fabricated on established, trailing-edge technology, such as sensors, microcontrollers and power components.

Even in 2013, where CPUs with 22nm transistors and mobile SoCs with 28nm transistors represent the current state of the art, some 40% of all silicon used to manufacture chips goes into mature devices fabricated on 200mm wafers. That’s typically 0.18-micron designs or larger. And much, if not most, of that is coming from pure-play foundries.

At the top of that second-tier foundry market, Israel’s TowerJazz, for example, has found a relatively comfortable niche making high-speed devices for a broad range consumer applications utilizing 0.13-micron designs and larger. It also makes CMOS image sensors with 0.16- and 0.11-micron design rules. In terms of financials, this has translated to record revenues: last year TowerJazz posted revenues of $638.8 million, an increase of 5% over the previous year.

Freeman suggested there are plenty of opportunities for these second-tier foundries. The so-called “Internet of Things,” for example, is a major driver behind sensor applications, as it is for the controllers needed to coordinate the data these sensors produce—data that can be managed via mobile Internet devices. These supplemental and complementary applications typically don’t need cutting-edge technology.

As has always been the case in the foundry industry, as leading-edge technology becomes trailing-edge, there will be new opportunities for second-tier foundries, as well. Some of the larger second-tier foundries eventually may have the opportunity to compete with first-tier companies head-to-head with 28nm capacity if they have deep-enough pockets to invest.

In the bifurcated smartphone market, for example, low-end smartphones that originally utilized chips manufactured with 40nm technology soon will migrate to chips with 28nm technology, as capacity ramps and it becomes even more cost effective, said Applied’s Ta. Even as the leading-edge players are driven beyond the 28nm node and the adoption of 3D gate architectures, the industry could very well see an extended 28nm node, driven by this market for lower-end smartphones and other mobile devices, she said.

But What About …
Things rarely ever prove to be so clearly defined in the chip industry. With players such as Samsung, Intel and IBM among others flirting with the foundry business, and some of the larger first-tier foundries suffering the same financial headaches that have plagued the IDMs in the past—problems that drove some of them to a fabless model in the fist place—there are some significant unknowns.

While 3D, high-k metal gate architectures, i.e, finFETs and the like, seem to be the wave of the near future, there are still those in the industry that tout the efficacy of fully depleted silicon-on-insulator (FD-SOI) as either an alternative to complement to 3D gate technology, for example.

IBM and its technology alliance partners have considered FD-SOI as a possible outcome of the semiconductor technology roadmap in the near future, Ta noted. “We see most of the effort on the finFET/Intel approach, but some of our customers are still talking about SOI,” perhaps used in some combination with finFETs, she added.

Gartner’s Freeman noted that Intel’s finFET devices are already fully depleted devices, although SOI could conceivably provide a bit less leakage; as such it may be an option at future nodes. Given the transistor speed and power usage achieved by its 22nm Atom processors, which are manufactured on top of bulk silicon technology, that seems unlikely though for Intel and those choosing to follow its lead. Freeman further observed that GlobalFoundries, once a proponent of FD-SOI, has backed off somewhat, although some of its largest customers remain committed to an FD-SOI strategy for the foreseeable future. IBM, for one, has publicly stated it will use FD-SOI, finFETs and stacked die together at future nodes.

But what does this mean for the leading-edge foundries? As always they will have to be able to manufacture what their customers want. It may be that some chipmakers will choose to go the FD-SOI route and that could prove a competitive opportunity for any foundry.

Another wild card that the top-tier foundries will need to take into account is the overlapping of technology nodes, which may become more pronounced with the extension of the 28nm node coupled with the rush to get 20nm devices into production. “It’s happening faster than previous node transitions have happened,” Applied’s Ta, noting that it’s driven by the low-power promise of finFETs. In the past node transitions typically took two to 2.5 years; “This time we may see a 1.5 year transition to finFETs,” she added.

Another question mark in the foundry market itself is SMIC. While most would still classify the Chinese foundry as a top-tier foundry, it is in a very real way straddling the gap between first and second tier. The company, once relatively close behind TSMC and UMC, has foundered in red ink and legal woes in recent years. While it has subsequently experienced an impressive turnaround financially under the helm of current CEO Tzu-Yin Chiu in 2012, it’s capital expenditures fell dramatically, even as capacity utilization hit 95% in Q2, and it is well behind its rivals in terms of technology.

Customer tapeouts of 28nm devices won’t take place until the end of this year; One of SMIC’s largest domestic customers, Spreadtrum, already has been forced to move to rival TSMC to meet its current plans for 28nm devices.

SMIC’s Chiu has said that the company’s 28nm technology will include both standard polysilicon oxynitride devices and high-k metal gates, and that it has plans to manufacture finFET devices at the 20nm node. In the meantime, it has found a saving grace in applications typically manufactured by second-tier players: smart cards, CMOS image sensors and power management chips.

Which way will SMIC go? Will it continue its impressive turn around by abandoning the leading edge or will it continue to play technological catch up? Or perhaps a little bit of both?

Time will tell. But it’s certainly an interesting time for the foundry business, and certain that for the foreseeable future the pure-play foundries will have to work hard at the cutting edge of semiconductor technology.

By Mark LaPedus
A year ago, chipmakers were reeling from a severe shortage of 28nm foundry capacity, prompting foundries to ramp up their fabs at a staggering pace.

At the time, foundries were unable to keep up with huge and unforeseen demand for mobile chips. The shortfall was also caused by low yields and the overall lack of installed 28nm capacity.

Today, the 28nm crunch is largely over. The foundries have caught up with the demand and customers no longer are feeling the pinch. And as it turns out, 28nm is a sweet spot for many devices and the technology will remain a long-lasting node.

However, the overzealous foundries may have expanded too fast. In fact, there are some signs of a possible foundry glut, and falling fab utilization rates, for 28nm and other processes in 2013. “I don’t see a shortage problem,” said Samuel Wang, an analyst at Gartner. “But overall utilization rates for advanced technologies will go down this year.”

Mobile chipmakers represent the biggest customers for foundries, but pockets of the business are cooling off to some degree. So, unless there is a steep upturn in the near term, the foundry market may quickly turn into a buyers’ market in 2013. Average selling prices for wafers could steadily drop, putting a squeeze on foundry margins.

Besides 28nm, foundries are simultaneously developing 20nm planar and 14nm-class finFETs. In doing so, foundries are moving toward the long-awaited “virtual IDM” model, where vendors and customers collaborate more closely under the same roof.

The shift towards the “virtual IDM” model is easier said than done, however. “The foundries will have some obstacles,” said Robert Bruck, vice president and general manager of the Technology Manufacturing Engineering Group at Intel. “Design, process technology, development and equipment costs are going up.”

As the costs and challenges mount, there are signs that the leading-edge foundry business is ripe for a shakeout. Currently, there are six companies that provide leading-edge foundry services in one form or another: GlobalFoundries, IBM, Intel, Samsung, TSMC and UMC.

28nm glut?
In total, the IC market is expected to increase 6% in 2013, compared to a drop of 1% in 2012, said Bill McClean, president of IC Insights. Capital spending is expected to fall 10% in 2013, but foundry CapEx will remain flat this year, he added.

For 28nm alone, the foundries had a total capacity of 200,000 wafer starts per month (wspm) by the end of 2012, according to Barclays Capital. In 2013, the foundries are expected to add an additional capacity of 75,000 to 100,000 wspm for 28nm, according to Mike Splinter, chairman and chief executive of Applied Materials.

And at 20nm, the foundries are expected to have a total capacity of 25,000 wspm in 2013, Splinter said in a recent conference call. Most of that capacity will be added in the second half of 2013, he said.

Splinter projects that the worldwide wafer fab equipment (WFE) market will be flat to minus 10% in 2013, up from minus 5% to minus 15% from his previous forecast. “We think the foundries will be down, but not as low as we expected,” he said.

CapEx race
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is showing no signs of a slowdown. The world’s largest foundry vendor has increased its capital spending from $8.3 billion in 2012 to $9 billion or more in 2013.

For 28nm, TSMC is expanding its capacity threefold in 2013 over 2012, said Morris Chang, chairman and chief executive of TSMC. In 2012, the polysilicon version of 28nm represented 100% of TSMC’s output. TSMC is expanding its 28nm high-k/metal-gate technology, which will reach the crossover point in the third quarter of 2013, he said.

The company also sees strong demand for 20nm. Apple will have its upcoming 20nm A7 application processors made on a foundry basis by TSMC, according to Barclays Capital, which noted that Apple is switching foundry vendors from Samsung to TSMC.

Meanwhile, GlobalFoundries, the world’s second largest foundry vendor, has set its capital spending budget at $3.5 billion in 2013, said Ajit Manocha, chief executive of GlobalFoundries. In 2012, GlobalFoundries’ capital spending hit $3.2 billion, according to Barclays.

The spending will help GlobalFoundries’ efforts to become more of a “virtual IDM.” In January, GlobalFoundries announced plans to build a multi-billion dollar R&D facility at its Fab 8 campus in Saratoga County, N.Y. The company’s new Technology Development Center (TDC) will help accelerate its 10nm and 7nm process development.

The TDC will also house part of GlobalFoundries’ stacked-die packaging and advanced photomask efforts. As photomask complexities soar, “some customers want a turnkey solution,” Manocha said.

Within its new 300mm fab in New York, the company has begun ramping up 28nm and 20nm processes. In 2013, Fab 8 is expected to expand from 10,000 to 30,000 wafers a month. “That’s still on plan,” he said. “We are also expanding our fab production in Dresden and Singapore.”

In total, GlobalFoundries will offer five technology platforms: bulk planar, bulk finFET, super-steep retrograde well (SSRW), FD-SOI (minimum) and FD-SOI (maximum). Customer tapeouts for its 14nm-class finFETs are expected in 2013, with production slated for 2014.

The maximum version of FD-SOI is tuned for specific applications, said Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries. Meanwhile, the minimum version is a simple and an “out of the box” FD-SOI technology, Kengeri said.

The company will provide FD-SOI wafers on a foundry basis for STMicroelectronics and other customers. GlobalFoundries’ 28nm FD-SOI process will move into risk production in the fourth quarter of 2013, with production slated for the first quarter of 2014.

Meanwhile, amid the apparent loss of a major customer in Apple, Samsung has cut its logic capital spending from 8 trillion Korean won in 2012 to between 4 trillion and 4.5 trillion Korean won in 2013, according to Barclays. Apple accounts for roughly one-third of Samsung’s logic capacity.

Samsung’s main logic/foundry fab is called S1, which is in Korea. S1 is making 28nm devices and is capable of low-volume finFET production. “S1 has more than doubled its size over the last year,” said Ana Hunter, vice president of foundry services at Samsung Semiconductor.

In Austin, Texas, Samsung has two 300mm fabs, plus a copper metallization facility. One fab is a foundry/logic plant. The fab, dubbed S2, has been a dedicated foundry plant for Apple. The other fab in Austin was previously a NAND facility. Last year, Samsung converted that fab from NAND into a 28nm logic/foundry plant.

In 2012, the company put on the brakes on its new S3 fab, a 300mm plant in Korea. “S3 resumed construction at the end of January,” said Christian Gregor Dieseldorff, an analyst at SEMI. “Equipment may begin to move in by mid-year. I think this may be the earliest.”

The S3 fab, which is expected to ramp up in 2014, will manufacture 20nm planar devices and 14nm-class finFETs. With process design kits available today, Samsung is expected to sample finFETs in 2014. In addition, the company has deployed “training teams” to help customers with their finFET designs, Samsung’s Hunter said.

The complexity of new and advanced designs will require more handholding between the foundries and their customers. “The collaboration has to get deeper with customers,” she added.

In moving towards the virtual IDM model, the foundries face some challenges. “There are very large investments that are required,” Intel’s Bruck said. “How do you accelerate the yield learning? What about the IP issues? Another aspect in terms of the foundry model is the delay that we are seeing in terms of revenue on the leading-edge.”

All chipmakers, including Intel, face the same challenge: How to keep up with the soaring R&D costs associated with the new and emerging technologies? “R&D is weighing on every level on the supply chain in this industry,” he added.

Foundry companies are keeping a close eye on Intel. To date, Intel is only providing foundry services to a limited customer base, and shows no signs of expanding the offering to a broader audience. So far, the chip maker is providing its 22nm finFET technology on a foundry basis to flow processor supplier Netronome and two FPGA vendors, Achronix and Tabula. In addition, Intel recently announced capital spending of $13 billion in 2013, including $2 billion for 450mm development.

Meanwhile, Taiwan foundry vendor United Microelectronics Corp. (UMC) continues to fall behind, as the company said it is having yield issues with its 28nm process. In addition, UMC recently said it will move directly from 28nm to 14nm finFETs, thereby skipping the 20nm node.

By Ann Steffora Mutschler
Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node.

“They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant of this shape or this line width or whatever that is creating a yield problem or weak patterns,” observed Michael White, director of product marketing for Calibre physical verification at Mentor Graphics. “Starting at 40nm, even more so at 28nm and that much again at 20nm, is much more orientation-specific layout because folks are using more off-axis illumination. You pay a huge penalty for having optimized the aperture in your scanner for things that are oriented north-south. If you’ve got structures that are east-west they’re not going to resolve as well.”

One approach to deal with these issues termed ‘bad pattern flow’ is based on the idea that the designer can almost do anything they want, but certain 2D patterns are walled off as being bad and forbidden.

Coming at the problem from another perspective is the concept of ‘good pattern flow,’ based on the premise that, “in the future, maybe not everything is going to be manufacturable anymore,” explained Ya-Chieh Lai, engineering director at Cadence. “So the designer is going to be much more constrained moving forward, and the space of the design is really that most things are actually not going to print very well anymore. There’s a sense that maybe we need to have a better understanding of which things do manufacture well and come up with a set of patterns to represent that.”

While not in use at 20nm, this good pattern flow is being readied for the 14nm and 10nm nodes when design rule restrictions become even more severe. But to be enabled in the design flow will require the whole ecosystem to come together, he said.

“We’re working hard on having the core capabilities and tools. We need to work closely with the foundries, because they’re ultimately the source of all of these patterns and a lot of this analysis, to provide the right tools and capabilities to do the kinds of analyses they need to do. We also have to work in conjunction with the design side tools to enable this. This is all a work in progress.”

Specifically, Manoj Chacko, product marketing director at Cadence, pointed out that just as with bad pattern usage, the value to the designer of a good pattern flow is at the routing stage. “Find the issues early on and remove them before going through the signoff. The good pattern flow also mostly fits with the routing side and enforces certain patterns and makes the router enforce certain topologies.”

In terms of where the tools are now, work is being done with the foundries to make sure there is understanding about what the patterns are and how they are used. “A key part of what we are working on here is pattern analysis,” said Lai. “There’s been a lot of talk about pattern matching, but pattern analysis is a bigger story about understanding your layout. The foundries need to understand what designers are doing, be able to understand what patterns are in the design, what are the common cases and the outlier cases to make sure their manufacturing processes are tuned to be able to print what the designers are actually doing. A big part of that is analyzing what is actually in the design.”

Pushback is possible
Mentor’s White expects significant pushback to the good pattern flow strategy. “Over the last couple of years as we’ve been moving pattern matching out into the mainstream use for physical verification, we have some folks who love the ease of use of pattern matching and so on, and their foundry was headed down the path of trying to use more pattern matching to describe actual design rules. The frustration was that, ‘If I’m using patterns to describe only a very finite, small set of things that are manufacturable, you’re taking the design freedom away from the designer.’ They’d far prefer to have the foundry characterizing a broader application space of layout and maintain the designer’s freedom rather than solely focusing their attention on a smaller set of patterns that are known manufacturable.”

Lai agreed there’s always tension about being as restrictive as possible. “If it were up to the foundry they’d just want you to print grading—it’s just going to be straight lines because they know they can print that. But the designers want more flexibility to draw what they need to draw. So what we’re trying to do with the good patterns is to say, ‘We’re going to be as restrictive as possible but then we’re going to allow certain things to be used that would otherwise have been restricted by these restrictive design rules.’ That way it really is meant to help the designer where instead of putting on the brakes and saying, ‘No, you can’t do anything except use these very straight repeated structures,’ we are saying there are going to be certain things that are going to be allowed. These are allowed constructs that you as a designer can put in because this is what you need to make your design work, but everything else is going to be very locked in.”

At the end of the day, “the goal is to minimize patterning,” said Subramani Kengari, vice president of design solutions at GlobalFoundries. “But you also have to optimize a solution. That’s the main reason we’re using wide power rails on standard cells.”

Another consideration: As it stands, not all of the metal layers in a design at 20nm, or even the hybrid 20nm back-end of line (BEOL) process are coupled with 14nm finFETs. But as Moore’s Law continues, more layers will have to be at least double patterned, and with 14nm BEOL some parts of the chip will have to be triple or quadruple patterned.

With this just one example of the complexity that will be faced, a good pattern flow seems more reasonable. And given that designs are becoming much more regular at these advanced nodes is one reason a good pattern flow even becomes a possibility.

To meet rapidly growing demand for logic products, Samsung Austin Semiconductor LLC said today it would to invest about $4 billion to renovate its existing fab to accommodate full System LSI production.

The remodeled fab will produce mostly state-of-the-art mobile SoCs on 300mm wafers at the 28nm process node with approximately 2,500 construction workers and equipment vendors required to retrofit the facility and set up the equipment, the company said in a statement.

Work on the renovation is set to begin this month, with mass production to begin in the second half of 2013.

Dr. Woosung Han, president of Samsung Austin Semiconductor said the company is pleased to extend its presence in Austin and reinforce Samsung’s capacity for highly advanced logic products. The added ability in production is meant to allow customers to better respond to market needs.

This marks the largest single foreign investment ever made in the state of Texas. Samsung’s total investment in Samsung Austin Semiconductor since 1996 will exceed $13 billion.

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By Mark LaPedus
The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond.

Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography.

The sea of change likely will add to the burden on the foundries, which are already under stress as they continue to do more of the R&D and heavy lifting for their customers. At present there is debate about what changes will be needed for this extra load, as well as the looming inflection points on the process and transistor fronts. But the future seems clear in one respect—some changes will be needed.

Intel has taken a big lead in the process race and the foundries are struggling to keep up. In addition, the cost-per-transistor curve has been falling at about 29% per node to enable cheaper systems. At 28nm and 20nm, however, the curve is leveling off at the foundries.

“The fabless companies at the leading-edge, such as Nvidia and Qualcomm, are visibly concerned about their foundries’ ability to keep up with Moore’s Law,” said G. Dan Hutcheson, president of VLSI Research. “To stay in the game, they need a steady decline in cost-per-transistor. If (the curve levels off), this certainly puts into question the common wisdom that the fabless-foundry model is impenetrable.”

The pressure resides squarely on the leading-edge foundries, GlobalFoundries, Samsung, TSMC and UMC, to keep up and deliver. Outside of Intel, vendors face a challenging transition from today’s planar technology at 20nm to finFETs and other architectures at 14nm and beyond.

They also must select between various CMOS technologies to enable scaling. Foundries are leaning towards bulk technology for planar at 20nm and finFETs at 14nm. A rival camp has made a case for silicon-on-insulator (SOI) technology. On the transistor front, there is talk about a hybrid finFET/planar approach. SuVolta has a new planar transistor option. And 3D stacked devices provide yet another avenue.

It’s unclear which technologies will emerge as the winners or losers. What is clear is that only companies with deep pockets can afford to participate. At 22nm, a fab runs $6.7 billion, process R&D is $1.3 billion, and design costs are $150 million, according to GlobalFoundries. And it will cost a staggering $32 billion in total process and tool R&D alone to develop 450mm fabs, according to VLSI Research.

Nonetheless, the fabless-foundry model appears to be far from broken, and predictions about the death of foundries seems greatly exaggerated. The pure-play foundry market is projected to reach $29.6 billion in 2012, up 12% from 2011, according to IHS. This business will grow by 14% in 2013, with double-digit growth continuing in 2014 and 2015, they said.

20nm challenges
Still, the 20nm node represents a pivotal juncture. Intel has made the shift from conventional planar transistors at 32nm to 3D finFETs at 22nm. For foundries, 20nm represents the last node in the planar era, because planar is beginning to suffer from undesirable short-channel effects.

And previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process. “As we move to 20nm, the fundamental differentiation between high-performance and low-power processes is going away,” explained Mojy Chian, senior vice president of design enablement at GlobalFoundries.

This move, coupled by delays in past nodes, prompted some industry pundits to imply that the fabless-foundry model is somehow broken. Chian dismissed the notion, saying the “fabless-foundry business is thriving.”

So what will keep the fabless-foundry model viable? There must be more collaboration and a new mindset, in which the foundries must change from being mere manufacturing partners into virtual IDMs, Chian said. “New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the time-to-market,” he said.

Vendors must also make some tough choices. On the CMOS front, for example, the foundries will generally move to conventional bulk silicon at 20nm, due to cost. GlobalFoundries is in the bulk camp, but it will also make select chips for IBM and STMicroelectronics using fully depleted SOI (FD-SOI) at 28nm and 20nm.

Regarding SOI, Soitec is offering another CMOS technology option. It provides SOI for planar (FD-2D) and finFET (FD-3D) devices. FD-2D has 241 process steps, compared to 328 for bulk, according to Soitec. SOI wafers are more expensive, but IC makers can offset the costs with fewer process steps, more performance and less power, said Steve Longoria, senior vice president of strategic business development at Soitec.

Jeff Lewis, senior vice president of marketing and business development at SuVolta, said the industry needs a new solution besides bulk and SOI at 20nm. “The cost-per-transistor is higher at 28nm than 40nm/45nm,” Lewis said. “The problems get worse for the 20nm node due to double patterning.”

Another problem is transistor threshold voltage variation, which is caused by systematic and random variations, he said. A phenomenon called random dopant fluctuation (RDF) causes more than 70% of all random variations at 65nm and the problems are getting worse at each node. “In scaling, you start to get mismatches from one transistor to another,” Lewis said. “So the threshold voltages start to vary.”

To solve RDF and other problems, SuVolta recently rolled out a new transistor option that extends conventional bulk CMOS technology. SuVolta’s Deeply Depleted Channel (DDC) technology works by forming a deeply depleted channel when a voltage is applied to the gate.

Beyond 20nm
The problems continue to mount beyond 20nm. It’s unclear if EUV will be ready for the 14nm node. So, IC makers must contend with costly multi-pattering schemes. On the transistor front, Intel has made the migration to finFETs, but its technology has been a hot topic of discussion. Some “have painted Intel as being in trouble with tri-gate because images from a tear-down showed the fin was not squared off, but more shaped like a half-oval,” VLSI’s Hutcheson said.

Others have shown more vertical fins. “It’s very doubtful that Intel is in trouble,” Hutcheson said. “To get a squared off shape would be easy, but it adds steps, hurts yields, and dramatically increases cost.”

Intel may have made some tradeoffs to solve one bulk finFET challenge: height variation. In finFET production, there is an etch step, followed by a back-fill oxide process, and then an implant for junction isolation. The hard part is to make fins with consistent heights during the etch process.

Because of height variability, there are fears that the foundries could struggle making bulk finFETs with any consistency. In response, one foundry claims to have overcome some of these obstacles. According to a paper at the recent IEDM, GlobalFoundries implemented a dual shallow trench isolation (STI) process to ensure fin height control. Its high-k/metal-gate scheme also helped construct “tall/narrow” fins with less doping for better RDF, according to the paper.

FinFETs provide a 40% improvement in power reduction, but the technology still doesn’t put the cost-per-transistor back on the 29% reduction curve. “You are getting a significant power advantage,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “It’s still a challenge to translate that to a die cost reduction.”

All told, the industry should take a harder look at SOI, said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. “FD-SOI is a fairly simple process, but there is a cost penalty,” Patton said. “When you get to finFETs, it’s a different story. The cost issue becomes neutral between bulk and SOI. Variability is also an advantage for SOI for finFETs.”

In the SOI model, “you place your order to the substrate supplier,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that promotes SOI. “The height of the fin is pre-determined. It’s pre-made for you.”

Fin variability in bulk finFETs is about 140% to 170% higher, versus SOI finFETs, according to the SOI Consortium. In the front-end-of-the-line (FEOL) process alone, SOI finFETs have 56 process steps, compared to 91 for bulk finFETs, the group said. In total, the FEOL cost for SOI finFETs is $561, compared to $805 for bulk, they said.

Still, GlobalFoundries, TSMC and Samsung are banking on bulk finFETs at 14nm for two reasons. First, it’s unclear if the SOI wafer suppliers can meet demand during crunch times, said GlobalFoundries’ Kengeri. “Historically, customers are not used to designing in SOI. They are comfortable designing with bulk,” he said.

What’s next?
Beside traditional finFETs, there is also talk about a hybrid approach. In this concept, chip makers would combine finFETs and planar devices on the same chip. The planar devices could include analog IP. “This is not easy to do,” Kengeri said. “It’s a complicated process.”

A more likely scenario is that current finFET technology would be scaled at least two generations to 10nm, he said. Then, at 7nm or before, the industry is looking at various next-generation finFETs to solve the mobility problems. The candidates include quantum well finFETs, PMOS germanium finFETs, and SOI. “From a research point of view, we’re looking at everything, but nothing is settled,” Kengeri said.

By Mark LaPedus
Faced with huge and unforeseen demand at the 28nm node, leading-edge foundries are scrambling to play catch-up and are boosting their fab capacities at a staggering pace.

But analysts warn that 28nm foundry capacity will be tight throughout 2012, and perhaps into 2013, putting some chipmakers in a pinch. Many blame the 28nm foundry capacity shortfall on a combination of three factors: low yields, lack of installed capacity, and simply underestimating demand. Much of the 28nm demand involves chips for smartphones, tablets and notebooks.

Acknowledging it didn’t have enough capacity in place, Taiwan Semiconductor Manufacturing Co. (TSMC) has responded and now plans to produce 10,000 more wafer starts per month (wspm) at 28nm than originally expected. Rival foundry Samsung Electronics is currently converting two NAND flash lines—one in Korea and another in Austin, Texas—into 28nm foundry capacity. And GlobalFoundries and United Microelectronics Corp. (UMC) are also expanding their 28nm capacities.

“Despite increases in spending by leading foundries, demand for 28nm chips will likely outstrip supply for much of the year,” said G. Dan Hutcheson, chief executive of VLSI Research. “While Apple will get all the 28nm chips it needs, other smartphone makers could be forced to postpone increases in production until more supply becomes available.”

For 28nm, the foundries in total are expected to have a capacity of some 65,000 wspm in 2012, according to Barclays Capital. At 28nm, the foundries are projected to have a total capacity of 300,000 wspm when capacity is fully reached in 2013, according to Barclays. In comparison, total foundry capacity has ranged from 200,000 to 250,000 wspm per node in previous generations, meaning that 28nm could become the largest node in history in terms of volumes.

The 28nm node is emerging as the sweet spot for select, leading-edge products, due to cost and its low-power attributes. Some chipmakers could prolong their efforts at 28nm before migrating to the more expensive and difficult 20nm node.

“We are seeing strong demand for 28nm,” said Michael Noonen, senior vice president of worldwide sales and marketing at GlobalFoundries. “Because of the solid value proposition of this versatile platform, we believe 28nm will be a long-lasting node.”

The big question is whether the foundries will overbuild at 28nm in 2012, causing the segment to fall into an overcapacity mode in 2013. There are some indications the foundries are expanding too fast and customers may be inclined to double order to garner enough wafers.

28nm shortages emerge
Shortages of 28nm foundry capacity, and to a lesser degree, 32nm technology, have been noticeable for months—and for good reason. There is typically an early learning curve for yields at the beginning of each process node.

But the market recently went into panic mode, when Qualcomm disclosed it could not meet demand for its 28nm cell-phone chips throughout 2012 due to unforeseen demand. The shortages involve 28nm parts based on a conventional polysilicon gate stack and not high-k. Initially, Qualcomm opted to use polysilicon at 28nm for cost reasons. In contrast, the FPGA houses elected to use high-k to get more performance.

To meet demand, Qualcomm plans to engage with multiple foundries to make up for the 28nm shortfall. Besides using its key 28nm foundry, TSMC, Qualcomm is now doing business with GlobalFoundries, Samsung and UMC.

Besides Qualcomm, Altera and Nvidia say 28nm capacity is tight. But two others, Advanced Micro Devices (AMD) and Xilinx, insist there is ample 28nm capacity.

Some chip makers reacted quicker to meet 28nm demand. Others weren’t so lucky. In a recent conference call, Jen-Hsun Huang, president and chief executive of Nvidia, said the company will not be able to meet demand for its new 28nm graphics chips throughout 2012. TSMC’s yields are “fabulous” for the device, Huang said. “We under-planned the supply of 28nm. We need to fix that in the future,’’ he said.

Capacity trends
Chipmakers impacted by the 28nm shortfall may have overlooked another trend: Less leading-edge capacity is being built at each node. Prior to the 90nm node, many foundry vendors competed at the leading edge.

But as fab and process R&D costs continue to soar, the foundry business has experienced a dramatic shakeout. Fewer foundry vendors—as well as chipmakers—can afford to compete at the leading edge. And leading-edge foundries have become more conservative in capital spending. “The investments to go to the next node are not easy to justify,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries.

At 130nm, a fab cost about $1.45 billion, process R&D costs were $250 million, and design costs were $15 million, he said. But at 32nm, a fab runs $4.85 billion, process R&D costs are $900 million, and design costs are $100 million.

“The foundries are being very careful not to overbuild,” said Joanne Itow, an analyst with Semico Research. The net result is that “capacity was tighter at 45nm/40nm compared to 65nm. Capacity at 32nm/28nm is tighter than at previous process generations.”

Today, the foundries are responding to 28nm demand by adding capacity and improving their yields, according to Itow. “28nm capacity will be very tight in Q3,” she said. “The foundries should be able to meet customer demand for 28nm by Q4.”

In 2013 there are questions about what will happen. Some believe the foundries will go into overcapacity mode as demand subsides. Others say demand will remain strong, particularly for 28nm. Mike Splinter, chairman and CEO of Applied Materials said: 28nm “is going to be a long node. We think it will be strong in 2012. It will be strong in 2013.”

Foundries react to demand
During a recent conference call, Morris Chang, chairman and chief executive of TSMC, said the company is unable to meet 28nm demand and vowed it will catch up with customer orders by the first quarter of 2013. TSMC has not been struggling with its yields, but rather it did not have enough capacity in place to meet demand, he said.

In response, TSMC plans to expand its total 28nm foundry capacity to 350,000 to 400,000 wafers in 2012. That’s 10,000 wspm more than originally planned at 28nm.

TSMC is currently producing 28nm wafers in two 300mm fabs. This includes Fab 14 (phase 4 and 5) in Hsinchu. It is also making 28nm devices in Fab 15 (phase 1 and 2), located in Taichung. Another portion in Fab 15 (phase 3 and 4) moved into 28nm production in April. By year’s end, these two phases will churn out 50,000 wspm.

For months, GlobalFoundries has been in 32nm production in Fab 1 in Dresden, Germany. The company has begun ramping up 28nm production in Fab 1, a 300mm plant with a total capacity of 80,000 wspm. In addition, GlobalFoundries soon will move into 32nm/28nm production in Fab 8, its new 300mm fab in New York. Fab 8 is capable of making 60,000 wspm.

Meanwhile, Taiwan’s UMC has begun ramping up 28nm production in 12A (phase 3 and 4), located in Tainan, Taiwan, said Christian Gregor Dieseldorff, an analyst with SEMI.

And not to be outdone, Samsung’s S1 fab in Korea is ramping up 32nm/28nm logic processes for foundry customers, including Apple. SEMI’s Dieseldorff also said Samsung is converting its Line 14 in Giheung, Korea from NAND to 28nm logic capacity.

Samsung, according to Barclays Capital, also is converting a NAND line in Austin, Texas, to 28nm foundry capacity. That line will produce 10,000 wspm a month for Qualcomm, and another 10,000 wspm for other customers, according to the firm.

Claiming it has a leg up in the race to provide leading-edge foundry services, GlobalFoundries said its Fab 1 in Dresden, Germany has shipped a cumulative total of 250,000 32nm High-k Metal Gate (HKMG) wafers which “represents a significant lead over other foundries in HKMG manufacturing.”

“Early in 2011 we met significant challenges in early yield learning on 32nm HKMG,” said GlobalFoundries CEO Ajit Manocha. “However, we made several organizational and operational changes in the second half of the year that led to a dramatic increase in production velocity and major breakthroughs in yield learning. And since our 28nm technology uses the same HKMG implementation as 32nm, AMD and other customers will benefit greatly from our high-volume ramp of leading-edge APUs at 32nm.”

AMD president and CEO Rory Read said “In just one quarter, we were able to see more than a doubling of yields on 32nm, allowing us to exit 2011 having exceeded our 32nm product shipment requirements. Based on this successful ramp of 32nm HKMG, we are committed to moving ahead on 28nm with GlobalFoundries.”

GlobalFoundries recently completed construction of an additional wafer manufacturing facility at Fab 1 in Dresden designed to add capacity at 45nm and below. The expanded Dresden fab has the potential to increase the overall output of the Fab 1 campus to 80,000 wpm once fully ramped.

The Dresden expansion project is adding more than 110,000 square feet of cleanroom space, and more than 50 percent of Fab 1’s production is now on HKMG technology. GlobalFoundries said that in addition to the 32nm technology, the company’s 28nm HKMG offerings are qualified and ready for design-in today.

ARM Ltd. said it is now offering the ARM Cortex-A9 MPCore Processor Optimization Pack (POP) for  the 28nm-SLP process technology from GlobalFoundries.  Intended for mobile, networking, and enterprise applications, the ARM POP 28nm-SLP for Cortex-A9 processors delivers performance up to 2 GHz in typical conditions.

Based on a high-k/metal gate technology, GlobalFoundries’ 28nm Super Low Power (SLP) platform is designed for power-sensitive mobile and consumer applications. It is based on the company’s established 32/28nm HKMG technology. ARM supports the GlobalFoundries 28nm-SLP process with its Artisan Physical IP Platform, which includes process-tuned nine track and 12 track multi-Vt standard cell libraries, power management kits, ECO kits, ARM Artisan high-density and high-performance optimized memory compilers, and GPIO through the ARM DesignStart online IP access portal.

“As consumer demand for high-performance, energy-efficient mobile devices increases, GlobalFoundries  and ARM are lowering the risk for customers by delivering optimized Cortex-A9 cores on a proven 28nm SoC process,” said Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries.

John Heinlein, vice president of marketing at ARM’s physical IP division, said the new 28nm POP “provides an easy next step to maintain a competitive edge.”

ARM POPs include three critical elements necessary to achieve an optimized ARM core implementation.  First, it contains Artisan Physical IP logic libraries and memory instances that are specifically tuned for a given ARM core and process technology. This Physical IP is developed through a tightly coupled collaboration with ARM Processor Division engineers in an iterative process to identify the optimal results. Second, it includes a comprehensive benchmarking report to document the exact conditions and results ARM achieved for the core implementation.  Finally, it includes a POP Implementation Guide that details the methodology used to achieve the result, to enable the end customer to achieve the same implementation quickly and at low risk.

GlobalFoundries, IBM, and Samsung Electronics will describe their technology offerings at the 2012 Common Platform Technology Forum, set for March 14 at the Santa Clara Convention Center.

Technologists from the three companies, which offer fab-compatible foundry services, will discuss their 28-, 20- and 14-nm processes, as well as innovations beyond 14nm. The event will include discussions of 450mm wafer manufacturing as well.

The forum’s Partner Pavilion, including EDA, IP, library, mask, packaging, and design services companies, will focus on the ecosystem of design enablement and implementation.

Registration is now open for the complimentary, one-day event at the Santa Clara Convention Center.