By David Lammers
Four years after making a shift to high-k dielectrics, the world’s largest semiconductor company has done it again, this time saying “bye bye” to the planar transistor design. Intel Corp. said Wednesday (May 4) it has succeeded in what senior fellow Mark Bohr called “a radical redesign” of the basic transistor structure at the 22nm node, moving to a tri-gate 3D structure that he said will support sharply lower operating voltages.
“The real advantage of going off into the third dimension is lower voltages, lower leakage,” Bohr said, adding that Intel estimates the wafer-level cost adder to be only 2-3 percent higher than for a planar transistor.
Bohr, along with Intel senior vice president Bill Holt and Intel Architecture general manager Dadi Perlmutter, demonstrated working servers, desktops and notebooks based on the upcoming “Ivy Bridge” line of MPUs based on the 22nm technology, expected to be in consumers’ hands early next year.
Bohr noted that all of the transistors on Intel’s 22nm products will use the tri-gate structure, casting aside earlier speculation that Intel might adopt a hybrid planar/finFET approach. (SemiMD reported on March 22 that Intel would go to a FinFET technology at the 22nm node.) And he said transistor performance could be varied by using six fins for some devices and only two on others, for example. The SRAM transistors would use a somewhat modified version of the tri-gate than the logic transistors, he added.
Bohr said Intel will again deploy a tri-gate design at the 14nm node, possibly with a taller fin to increase performance further. By going from a nominal 22nm design rule to 14nm, Intel may achieve a higher-than-normal increase in transistor density compared with previous technology transitions.
Bohr said Intel decided early on that for its 22nm technology it would need to move beyond the planar channel that has served the chip industry for the past 50 years. By wrapping the gate around a conducting channel that includes the top and two sides of the tall, narrow fin, Bohr said Intel is able to gain better control of the channel, drive more current, and sharply reduce power consumption.
Compared with Intel’s best 32nm planar transistors, the 22nm “3D” device achieves 37 percent higher performance at .7 V operation, a Vdd that is largely impractical for planar structures. Later in his presentation, Bohr said the tri-gate structure would deliver roughly the same gate delay, but at .2 V lower supply voltages, or 0.8 V. At the same voltage as a planar transistor, the tri-gate will deliver “dramatic performance gains,” Bohr said.
“A 22nm tri-gate can deliver the same performance as 32nm planar, but at 0.8V instead of 1.0V, providing more than a 50 percent active power reduction,” Bohr said.
Bohr gave the assembled reporters a short tutorial on transistor device physics, saying that with planar devices a weak voltage on the substrate layer prevented the optimum sub-threshold voltage swing. With fully depleted silicon-on-insulator (SOI) devices, Bohr said the main challenge was wafer cost. With the ultra thin body SOI technology which STMicroelectronics and others are promoting, Bohr said bringing the buried oxide layer much closer to the silicon surface requires close wafer-manufacturing controls. “Those extremely thin (silicon and BOX layer) SOI wafers are available, but they are very expensive, and pretty hard to get,” Bohr said. Intel’s estimate is that using a thin-layered SOI wafer would add 10 percent to the finished wafer cost. (The SOI camp argues that fewer isolation and other steps translate into fewer masks, equalizing the wafer cost adder.)
Source: Intel Corp.
Perlmutter said Intel can operate its products at lower voltages and get “way lower power, while still getting to half the transistor size” compared with the 32nm planar technology. Intel has struggled to get its Atom line of SoC products adopted, partly because of lower power budgets for the ARM-based mobile SoCs. Perlmutter said Intel would move more quickly than in the past, bringing the Atom-based products on to the 22nm manufacturing platform fairly quickly compared with the 45nm and 32nm generations.
The first products using the tri-gate transistors will be a dual-core Ivy Bridge design. But he said the mobile products supported by the Atom core need the tri-gate technology. “It is extremely needed. It delivers more ‘power-full’ performance and more ‘power-less’ power consumption,” he quipped.
Dan Hutcheson, CEO of market research firm VLSI Research Inc, said the shift to a tri-gate structure is “truly a historic event,” coming some 50-plus years after Bob Noyce, Jack Kilby and others developed the first planar transistors. “This is like delivering the advantages of two nodes in one,” Hutcheson said.
Dean Freeman, an analyst at Gartner Inc., said “this is a big coup for Intel.”
The early shift to a tri-gate architecture “does give Intel a crack at the mobile device market, as the power consumption is very good. The performance capability should blow ARM devices out of the water.”
TSMC, which manufactures many of the ARM-based SoCs for the mobile chipset vendors, will “follow Intel’s lead to finFETs, but likely at 14nm. I don’t think IBM will hit finFETs until 14 as well,” Freeman said.
There are several manufacturing challenges with finFETs, the Gartner analyst said. The lithography tools must be able to print the feature size with the required alignment. “It was thought that EUV was going to be needed for this but it is possible that the overlay ASML and Nikon are achieving now will allow them to be successful,” Freeman said.
Sidewall doping is another challenge. “While the plasma immersion does a fairly good job there have been concerns regarding uniform doping density on the side wall of the source and drain,” he said.
Sidewall roughness — always an issue at leading edge design rules — can be a particularly tough issue for finFETs during etching of the poly or silicon line, he said.
Intel said its 22nm Trigate design performs well at low voltage operation.