By Ed Sperling
Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation.

SMD: What’s changing in the ecosystem and how will it continue to change over the next couple process nodes?
Quan: If you look at 28nm, and even at 40nm, we started working with EDA companies with our design rule manual earlier than in the past. Version 1.0 is basically production. At 28nm, we started working with our partners on version 0.1, which is very early, then version 0.5 all the way up to 1.0. With 16nm finFETs, we’re now working on version 0.1. These can change every few days, so the commitment from Synopsys, Mentor and Cadence has to be very high because you have to have a way to synchronize these activities to get to the next version.
Lim: From a partnership perspective, there are multiple levels. There is a partnership in terms of tools, and there is a partnership in terms of IP. From the tools perspective, you have to start much earlier and you have to work hand-in-hand. In previous process nodes, the IP development started much later. Now, at 20nm and with finFETs, at any point in time that we can start we do it.
Kranen: If something is partially or sort of valid, it’s time to start.
Lim: It’s okay if it’s not done, but what we want is to be early to market. For our customers, time to market is critical. They want to see IP that is stable, characterized and validated. That’s why we have to start early. Also, if you think about 28nm, the time from tapeout to sample is three to four months. With finFETs, it’s six months. We don’t have time to wait. We have to start extremely early and tapeout as soon as possible. That way when samples come back we can start validating for our customers.
Kranen: Over the past two or three nodes, the customer gets engaged earlier, too. We’re doing the work together, we have to support the early customers, and the number of customers who are in early has gone up over time. At the leading edge it has gone from one or two to five, and now we’re working with eight or nine very early in the cycle. They’ve got to get in earlier, too, both on the IP and the tool side.
Buehler-Garcia: What’s changed is that the guys who were the lead people before aren’t in the same position today. Some large companies don’t do bulk anymore. And foundries like TSMC aren’t going to go beat up everything. Their job is to be a foundry. So getting in early and getting involved to make sure parts work is critical. The number of people who are working with double patterning is large. The early customers we worked with before understand the deck is going to change. That’s part of the deal, especially with a fabless model. You get the 0.5 deck from the foundry, 0.5 IP, 0.5 software, and it might not work exactly right. That’s part of the discovery. I’m a little concerned that some of these guys who are coming early are going to stress the partnership. There’s an expectation among everyone to do more better.
Quan: It used to be that a lot of customers could wait until it was all settled. Now they know they have to get involved earlier to do their test chip.
Buehler-Garcia: They might get that the process and the tools aren’t there, but you can’t get started without the IP.
Lim: A lot of this is about customer expectations and managing those expectations. The customers who have done it before with their own internal IP and libraries have experienced it. The customers know that when it’s 0.1 or 0.5 it may not work perfectly, but they still want to do it because it helps them get to market more quickly.
Buehler-Garcia: They understand what they’re getting into.
Kranen: The reality is that you have to do one spin just to figure out where you are, and then the second one is all about getting it right.
Buehler-Garcia: On the IP side of the house, the old model is that the IDMs did it all. And then we had everyone else. But some of the big IDMs are no longer involved. The guys who do it all with their own IP, they’re buying more. The entire market is moving to consumer-cycle time.

SMD: So along those lines, are companies still focusing on their own IP?
Kranen: They’re asking, ‘What’s not differentiated?’ They’re starting to understand that they don’t need to do the standard IP.
Quan: The first thing customers have to do is define a test chip for their first tapeout. Those are the ones they want to put the most critical IP on, and most of that is done in-house. Then they work backward, which is what drives the rest of us to know when a critical tool has to be available. If the rest of the IP can comes from outside, that also has to be on the road map.
Lim: There are shifts under way. It used to be that companies built everything from the ground up. Then came the fabless companies, and from vertical it turned horizontal. Now you’re starting to see more large companies doing the full SoCs themselves again.
Kranen: They’re going vertical from a systems perspective.
Lim: And the fabless companies are recognizing that it takes too much investment to do everything themselves, and their customers are doing the chips, too. There are two groups, the fabless companies and the system companies, trying to compete to get to the most advanced SoC in the fastest manner. That’s driving the time to market and more and more use of IP. In some areas, all of them are using the same IP.

SMD: Can an ecosystem keep up with IDMs—or even surpass the IDMs?
Kranen: It has the potential to exceed it.
Buehler-Garcia: There is no such thing as a true IDM anymore. The bill of materials on a smartphone shows that it’s all about time to market. They don’t care where the silicon is from. But who uses advanced technology now? It used to be the military, then it was supercomputers, then servers. Now it’s the consumer. And if it’s not ready by Christmas, you’re out.
Quan: Even on the innovation side, more brains are better. If you look at IDMs, they are more captive. There are very few new markets they try to develop for. If you look at foundries, the customers and the EDA partners and IP partners and all of those together, they will come out much better.
Kranen: The potential is there. The trick is coordinating it and making sure it comes in on time. You don’t want a customer asking for something too late in the cycle. That’s where you get into trouble. The customer may need a piece of IP in six months and what happens if it’s late?
Quan: That’s the discussion around coordination. How do you coordinate all of these parts and optimize interfaces?
Buehler-Garcia: But is there really an IDM anymore? Even the largest IDMs buy a boatload of IP. There are no IDMs like 10 years ago that were driving 90% of the requirements. Those requirements are being driven by five to seven customers these days, not one big one.
Lim: Everyone wants differentiation, too.

SMD: How close do you have to be to your partners in this ecosystem, and how much money does it cost?
Buehler-Garcia: If you’re not going to fund it and run your own program, then you need to partner with someone who will fund it for you and everyone else.
Quan: If you look at the R&D from TSMC and our customers and add all them up, that’s bigger than any IDM in history.

SMD: But is it all going together and being coordinated as a single budget?
Buehler-Garcia: No, it’s lots of individual pieces.
Quan: But if you look at the way we work with Synopsys, Mentor and Cadence, at 16nm, we’ve got all the legal commitments in place and all the companies have agreed to put in resources and time to commit up front. We put in hardware, software and a lot of stuff. There really is a lot of coordination going on.

GlobalFoundries VP Subramani Kengeri talks about progress and problems with advanced processes with Semiconductor Manufacturing & Design.

The 20nm process node represents a turning point for the electronics industry. While it brings tremendous power, performance and area advantages, it also comes with new challenges in such areas as lithography, variability, and complexity. The good news is that these become manageable challenges with 20nm-aware EDA tools when they are used within end-to-end, integrated design flows based on a “prevent, analyze, and optimize” methodology.

To download this white paper, click here.

By Ann Steffora Mutschler
Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node.

“They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant of this shape or this line width or whatever that is creating a yield problem or weak patterns,” observed Michael White, director of product marketing for Calibre physical verification at Mentor Graphics. “Starting at 40nm, even more so at 28nm and that much again at 20nm, is much more orientation-specific layout because folks are using more off-axis illumination. You pay a huge penalty for having optimized the aperture in your scanner for things that are oriented north-south. If you’ve got structures that are east-west they’re not going to resolve as well.”

One approach to deal with these issues termed ‘bad pattern flow’ is based on the idea that the designer can almost do anything they want, but certain 2D patterns are walled off as being bad and forbidden.

Coming at the problem from another perspective is the concept of ‘good pattern flow,’ based on the premise that, “in the future, maybe not everything is going to be manufacturable anymore,” explained Ya-Chieh Lai, engineering director at Cadence. “So the designer is going to be much more constrained moving forward, and the space of the design is really that most things are actually not going to print very well anymore. There’s a sense that maybe we need to have a better understanding of which things do manufacture well and come up with a set of patterns to represent that.”

While not in use at 20nm, this good pattern flow is being readied for the 14nm and 10nm nodes when design rule restrictions become even more severe. But to be enabled in the design flow will require the whole ecosystem to come together, he said.

“We’re working hard on having the core capabilities and tools. We need to work closely with the foundries, because they’re ultimately the source of all of these patterns and a lot of this analysis, to provide the right tools and capabilities to do the kinds of analyses they need to do. We also have to work in conjunction with the design side tools to enable this. This is all a work in progress.”

Specifically, Manoj Chacko, product marketing director at Cadence, pointed out that just as with bad pattern usage, the value to the designer of a good pattern flow is at the routing stage. “Find the issues early on and remove them before going through the signoff. The good pattern flow also mostly fits with the routing side and enforces certain patterns and makes the router enforce certain topologies.”

In terms of where the tools are now, work is being done with the foundries to make sure there is understanding about what the patterns are and how they are used. “A key part of what we are working on here is pattern analysis,” said Lai. “There’s been a lot of talk about pattern matching, but pattern analysis is a bigger story about understanding your layout. The foundries need to understand what designers are doing, be able to understand what patterns are in the design, what are the common cases and the outlier cases to make sure their manufacturing processes are tuned to be able to print what the designers are actually doing. A big part of that is analyzing what is actually in the design.”

Pushback is possible
Mentor’s White expects significant pushback to the good pattern flow strategy. “Over the last couple of years as we’ve been moving pattern matching out into the mainstream use for physical verification, we have some folks who love the ease of use of pattern matching and so on, and their foundry was headed down the path of trying to use more pattern matching to describe actual design rules. The frustration was that, ‘If I’m using patterns to describe only a very finite, small set of things that are manufacturable, you’re taking the design freedom away from the designer.’ They’d far prefer to have the foundry characterizing a broader application space of layout and maintain the designer’s freedom rather than solely focusing their attention on a smaller set of patterns that are known manufacturable.”

Lai agreed there’s always tension about being as restrictive as possible. “If it were up to the foundry they’d just want you to print grading—it’s just going to be straight lines because they know they can print that. But the designers want more flexibility to draw what they need to draw. So what we’re trying to do with the good patterns is to say, ‘We’re going to be as restrictive as possible but then we’re going to allow certain things to be used that would otherwise have been restricted by these restrictive design rules.’ That way it really is meant to help the designer where instead of putting on the brakes and saying, ‘No, you can’t do anything except use these very straight repeated structures,’ we are saying there are going to be certain things that are going to be allowed. These are allowed constructs that you as a designer can put in because this is what you need to make your design work, but everything else is going to be very locked in.”

At the end of the day, “the goal is to minimize patterning,” said Subramani Kengari, vice president of design solutions at GlobalFoundries. “But you also have to optimize a solution. That’s the main reason we’re using wide power rails on standard cells.”

Another consideration: As it stands, not all of the metal layers in a design at 20nm, or even the hybrid 20nm back-end of line (BEOL) process are coupled with 14nm finFETs. But as Moore’s Law continues, more layers will have to be at least double patterned, and with 14nm BEOL some parts of the chip will have to be triple or quadruple patterned.

With this just one example of the complexity that will be faced, a good pattern flow seems more reasonable. And given that designs are becoming much more regular at these advanced nodes is one reason a good pattern flow even becomes a possibility.

Semiconductor Manufacturing & Design sits down with Mentor Graphics’ Jean-Marie Brunet to talk about double patterning, finFETs, design rules at advanced nodes and why design for manufacturing (DFM) has suddenly become so popular.

Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges they present, and various solutions, including:

• DP design methodologies, current DP conflict feedback mechanisms, and how they can help designers identify and resolve conflicts.
• Effects on place and route (P&R) and new reqirements for physical design.
• Why LELE DP cuts and overlaps are critical to optical process correction (OPC).
• Mask misalignment and image rounding as new verification considerations.

To download this white paper, click here.

By Mark LaPedus
For years, silicon foundries have rolled out their respective leading-edge processes roughly on a two-year cadence.

The long-standing goal has been to keep foundry customers on a competitive price, power and performance curve. But as leading-edge chipmakers move from the 28nm node and beyond, the predictable process progression is changing. And the phenomenon of “node skipping” in the fabless-foundry world could reach new heights.

Two foundry vendors, GlobalFoundries and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), recently accelerated their respective 14nm-class finFET shipment schedules by a year or so. In effect, the companies have shrunk the process cadence between their planar 20nm and 3D-like finFET technologies to roughly a year.

Samsung is expected to follow a similar path. In many respects, the foundries appear to be luring customers into making the giant leap from 28nm (or above) processes to finFETs, thereby skipping 20nm. The reason is largely due to lackluster demand for 20nm planar, and they are aggressively marketing their finFET technologies right now.

Rival United Microelectronics Corp. (UMC) has a different strategy. UMC will move directly from 28nm planar to 14nm-class finFETs, bypassing the 20nm planar node. UMC recently licensed finFET technology from IBM, but it will stick with bulk CMOS. For its part, IBM will ramp up finFETs using silicon-on-insulator (SOI) technology.

The foundries are speeding up their finFET efforts for several reasons. First, there is a perception that the foundries are falling further behind Intel. The chip giant rolled out finFETs at 22nm and is offering the technology to select foundry customers. Intel plans to begin ramping up its 14nm finFET process by the fourth quarter of 2013.

Some chipmakers have been openly critical about the 20nm foundry planar process, saying the technology puts the industry behind the traditional performance curve. “I know some customers want more,” acknowledged Morris Chang, chairman and chief executive of TSMC, in a recent conference call.

So, at 20nm and beyond, chipmakers are weighing their options and exploring the trade-offs. “There will be customers that will skip 20nm to get to (finFETs),” Chang said. “I think there will be customers that will be light on one (process technology) and heavy on another.”

The benefits of finFETs are clear, but the industry is finally coming to grips with the challenges associated with the transistor technology. Cost, patterning and variation are just a few of the issues. The complexity will require more and deeper collaboration between foundries and their customers. “The challenge for us is to work across the ecosystem with our partners and have earlier tapeouts that are fully debugged and tested,” said Gregg Bartlett, senior vice president and chief technology officer at GlobalFoundries.

All told, the fabless-foundry model is still alive and well, but the business continues to change. Going forward, leading-edge foundries will offer fewer process derivatives. Customers will have fewer choices. And in the future, expect possibly one foundry to exit from the leading-edge process race, with more consolidation seen on the horizon.

Skipping around the IC world
At one time, most leading-edge chipmakers followed the natural progression of process technology nodes. The dynamics began to change starting around the 90nm node, when chipmakers migrated towards sub-wavelength lithography, low-k, design-for-manufacturing (DFM) and other technologies.

IC design and manufacturing costs began to soar. As the complexity and cost escalated at each process node, it was no longer a clear-cut decision to follow the natural cadence of process nodes. Chipmakers weighed the various technical and economic trade-offs.

Starting at 90nm, node skipping among chipmakers became the rule instead of the exception. For example, Netronome is currently shipping communications processors based on a 65nm process from TSMC. Instead of moving to 40nm or 28nm, Netronome recently decided to make a giant leap from 65nm to Intel’s 22nm finFET foundry technology. The decision, according to Netronome, was based on density, power consumption and cost.

Node skipping is expected to reach new heights at the 20nm planar process. The so-called “time-to-market” IC makers, such as AMD, Altera, Nvidia, Qualcomm, Samsung, and Xilinx, likely will make the traditional progression from 28nm to the 20nm planar node before moving to finFETs.

Many of the so-called fast-followers, such as Broadcom, Freescale, Marvell and LSI, are still on the fence. At a recent event, for example, a Marvell representative questioned the feasibility of the 20nm planar node, saying the technology has a “negative ROI.”

Previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process, thereby providing customers with fewer choices.

The 20nm planar node also brings some new and challenging technologies to the mix, such as double patterning and the introduction of a third layer of local interconnects called the middle-of-the-line. At 20nm planar, there is a performance boost over 28nm, but the transistor speeds slow down as operating voltage is reduced.

IC makers that moved from 40nm to 28nm have experienced a 35% average increase in speed and a 40% power reduction, said Jack Sun, vice president of R&D and chief technology officer at TSMC. In comparison, IC vendors that will move from 28nm to 20nm planar are expected to see a 15% increase in speed and 20% less power, Sun said.

With that in mind, there is a temptation to skip 20nm and migrate to finFETs. FinFETs take the traditional 2D planar design and turn the conductive channel on its side, resulting in a 3D “fin” structure surrounded by a gate that controls the flow of current.

Compared to 32nm planar, finFET transistors enable a 37% performance increase at low voltages and a power reduction of 50% or more, according to Intel. Intel’s own Tri-Gate transistor enables a steeper sub-threshold slope at around 80 mV/decade or below, compared to 100 mV/decade for leading-edge planar transistors, said Mark Bohr, senior fellow at Intel, at a recent event.

“Vdd scaling has slowed down. Leakage is an issue as geometries shrink,” said Srinivas Nori, director of SoC marketing at GlobalFoundries. “The value (that finFETs) bring is that it enables one to lower the Vdd. Leakage is better controlled. The variation of the Vt is also much better controlled.”

The benefits are easy to grasp, but the hard part is obvious. “If I was a designer, I would be worried,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that is promoting SOI. “If you go back to the standard way of doing things in bulk, and you want a transistor with a different Vt and that drives a different current, you printed different line widths. You just made a fatter transistor. And you paid a little a bit of a penalty in the capacitance,” Mendez said. “How the heck can do you that in finFETs? It’s impossible. So, to make finFETs, you go in quantum steps. The way you actually do this is that you put down one fin, two fins or three fins on a structure.”

Besides the quantum issues, there are other problems. “The fin height is now a huge variable. In a junction-isolated fin, I don’t know how that is accurately controlled. So, from my perspective, this is a tricky thing for an SoC guy to get around. I would imagine you would need pretty stiff design rules to account for this,” he said.

Because of fin height variability, there are fears that the foundries could struggle making bulk finFETs with any consistency. The SOI proponents are pushing fully-depleted SOI (FD-SOI), claiming the technology can reduce the process steps and variability with little or no cost penalty.

New roadmaps
The foundries are still pushing bulk, but they have changed their roadmaps. In September, GlobalFoundries rolled out its finFET technology, dubbed 14nm-XM, based on a “modular fin” approach. GlobalFoundries opted to marry a 14nm front-end fin with a 20nm planar BEOL flow. In doing so, the company has accelerated its finFET process by a year. Product tape-outs are expected in 2013, with production slated for 2014.

“Today, customers, IP vendors and the whole ecosystem can actually start working on finFETs,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “There are about 7,000 design rules that will carry over from 20nm planar to finFET. From a design point of view, the very early PDKs are almost the same as 20nm.”

Earlier this year, TSMC thought 20nm planar would become a popular node and announced a 20nm pilot line to prepare for the big ramp. But initial 20nm demand is lukewarm. TSMC claims to have 50 tape-outs for the technology, roughly one-fifth compared to that of 28nm.

TSMC’s 20nm pilot line is still on track for 2013. But last month TSMC accelerated its finFET risk production schedule from February 2014 to November 2013. Mass production is slated a year after its 20nm planar process. “This is a somewhat faster cadence than the previous generation,” TSMC’s Chang said.

Meanwhile, UMC said it has developed 20nm planar capability, but the company is not pursuing it as a mainstream process offering. Instead, it is more or less skipping 20nm and pursing finFETs. “After 28nm, finFET will be our focus,” said Shih-Wei Sun, chief executive of UMC, during a recent conference call.

By Mark LaPedus
The 14nm node represents an inflection point for leading-edge foundries.

The foundries hope to make a monumental shift from conventional planar transistors at 20nm to finFET structures at 14nm. And to accelerate their finFET efforts, leading-edge foundries are looking at hybrid integration schemes and “modular fin” strategies.

Using this approach, a foundry would devise a fin structure at the front-end with 14nm design rules. The fin structure itself is modular, meaning it can be plugged into a newly developed and corresponding 14nm back-end-of-line (BEOL) interconnect flow.

But by being modular, vendors also have the option to plug in the 14nm fin into an existing planar 20nm BEOL flow. This hybrid integration approach could enable a vendor to accelerate its finFET introduction date, but there are also some die-cost disadvantages.

“There are no challenges from a process point of view,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “What you are doing is taking a fin module and making it compatible at 14nm and 20nm.”

By going the modular fin route, foundries hope to provide fast and flexible solutions for customers. “It has to be competitive,” he said. Foundries appear to be taking a “modular fin” approach for good reason: They must speed up their finFET efforts to play catch up with Intel and satisfy increasing customer demand for the technology.

Challenges mount at 14nm
The foundries face some challenges to integrate “modular fins,” not to mention bringing up finFET structures in the first place. At 14nm, there are other manufacturing challenges, such as etch, deposition, inspection and lithography. The net result is that there must be a closer collaboration between foundries and customers. “The key is to have a tighter integration between product design and manufacturing,” Kengeri said.

Clearly, the leader in finFETs is Intel Corp., which is already using the technology for its microprocessors at 22nm. At that node, Intel is also providing foundry services to a limited set of fabless chip makers.

Right now, the foundries are still ramping up their 28nm processes, with planar at 20nm and finFETs at 14nm in the works. At 14nm, the industry is not banking on extreme ultraviolet (EUV) lithography. The EUV power source is simply not ready.

Instead, the industry is gearing up for 193nm immersion and multi-patterning. “If EUV was ready today, people would use it,” said David Hemker, chief technology officer in the corporate technology development group at Lam Research. “The industry is confident using double pattering.”

Beside lithography, there is another pressing issue for finFETs: variability. Intel proved that a chipmaker could ramp up finFETs using bulk CMOS technology. Attempting to follow Intel’s successful formula, the foundries have decided to extend bulk CMOS into the finFET era.

But because of fin height variability, there are fears that the foundries could struggle making bulk finFETs. “People are just waking up to this,” said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. The foundries should take a harder look at silicon-on-insulator (SOI) technology, which can reduce fin height variability, Patton said. And because there are fewer process steps with SOI-based finFETs, the traditional cost penalty associated with SOI disappears, he added.

The finFET transition also will cause a spike for process-control tools. Given the soaring costs of IC designs, there is little margin for error. It will become more critical to spot killer defects much earlier in the process.

One of the emerging areas in process control involves non-visual defects. Non-visual defects do not scatter light and are not detectable by current optical or e-beam inspection tools. “Up to 30% of yield loss in today’s fabs are not traceable to physical defects,” said Robert Newcomb, executive vice president at Qcept Technologies, a metrology tool vendor.

Non-visual defects are cropping up in some new and unforeseen areas in finFET designs. In development work for one customer, for example, Qcept’s tools detected horizontal defect patterns in the outer 20nm to 30nm of the wafer in a finFET design.

Get out the scorecards
And if that isn’t enough, chipmakers will need a scorecard just to keep track of the foundries and their latest finFET roadmaps. The nodes at which vendors will introduce finFETs are a bit misleading and don’t necessarily tell which company is ahead in the race.

For example, United Microelectronics Corp. (UMC) is rolling out finFETs at 20nm. UMC is marrying a 14nm front-end fin with a 20nm backend. Rival Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is talking about finFETs at the 16nm half-node. So far, Samsung is sticking to its plans to launch finFETs at 14nm.

GlobalFoundries, meanwhile, has devised a modular fin with 14nm front-end design rules, but it has not decided whether it will insert the structure to a 14nm or 20nm BEOL scheme. “We’ve been analyzing to see what is the right approach,” Kengeri said. “We may put it on 20nm. We may put it at 14nm. We may put it on both.”

In all cases, chipmakers still are able to devise new and innovative IC designs with finFETs. “To achieve this, there are many aspects of finFET technology,” he said. “Optimization and upfront planning are key. The ratio of contacted poly pitch, metal layers and fin pitch are critical. The choice of fin pitch will impact fin efficiency, resistance-capacitance, cost, process complexity, scalability and many other metrics. Therefore, it is important to architect the finFET process with a fin pitch optimal for both 20nm and 14nm and targeted for specific applications.”

Still, the modular fin strategy has some tradeoffs. The first option is to combine a 14nm front-end modular fin to a corresponding middle-of-the-line (MEOL) and BEOL flow at 14nm. The fin structure can be easily manufactured using 193nm immersion, multi-pattering and other steps.

The real challenge is to devise an entire new MEOL and BEOL infrastructure at 14nm, which could be an expensive proposition. Chip manufacturers could extend their existing physical vapor deposition (PVD) tools to devise the interconnect at 14nm. But for the capping layers, chipmakers may need to move to new deposition tools as well as materials like cobalt, said Sree Kesapragada, global product manager for metal deposition products at Applied Materials.

Until foundries bring up a new 14nm MEOL/BEOL flow, they may opt to go with the less expensive hybrid approach. This marries a 14nm fin with a 20nm planar MEOL/BEOL flow. The idea behind this approach is that foundries can leverage and use their existing and mature 20nm tools.

There are also some time-to-market and tool cost-of-ownership advantages with the hybrid approach. “There are some pros and cons,” Kengeri said. “You can bring up the technology faster.”

The disadvantage is that the die cost is roughly similar between a 20nm planar device and a hybrid 14nm/20nm finFET. “You don’t get the die cost advantage” of a homogenous 14nm finFET structure, he said. There also could be some integration challenges in terms of the different capacitances between the 14nm front-end fin and the 20nm planar BEOL. “It’s something you have to account for and model,” he said.

By Mark LaPedus
The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond.

Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography.

The sea of change likely will add to the burden on the foundries, which are already under stress as they continue to do more of the R&D and heavy lifting for their customers. At present there is debate about what changes will be needed for this extra load, as well as the looming inflection points on the process and transistor fronts. But the future seems clear in one respect—some changes will be needed.

Intel has taken a big lead in the process race and the foundries are struggling to keep up. In addition, the cost-per-transistor curve has been falling at about 29% per node to enable cheaper systems. At 28nm and 20nm, however, the curve is leveling off at the foundries.

“The fabless companies at the leading-edge, such as Nvidia and Qualcomm, are visibly concerned about their foundries’ ability to keep up with Moore’s Law,” said G. Dan Hutcheson, president of VLSI Research. “To stay in the game, they need a steady decline in cost-per-transistor. If (the curve levels off), this certainly puts into question the common wisdom that the fabless-foundry model is impenetrable.”

The pressure resides squarely on the leading-edge foundries, GlobalFoundries, Samsung, TSMC and UMC, to keep up and deliver. Outside of Intel, vendors face a challenging transition from today’s planar technology at 20nm to finFETs and other architectures at 14nm and beyond.

They also must select between various CMOS technologies to enable scaling. Foundries are leaning towards bulk technology for planar at 20nm and finFETs at 14nm. A rival camp has made a case for silicon-on-insulator (SOI) technology. On the transistor front, there is talk about a hybrid finFET/planar approach. SuVolta has a new planar transistor option. And 3D stacked devices provide yet another avenue.

It’s unclear which technologies will emerge as the winners or losers. What is clear is that only companies with deep pockets can afford to participate. At 22nm, a fab runs $6.7 billion, process R&D is $1.3 billion, and design costs are $150 million, according to GlobalFoundries. And it will cost a staggering $32 billion in total process and tool R&D alone to develop 450mm fabs, according to VLSI Research.

Nonetheless, the fabless-foundry model appears to be far from broken, and predictions about the death of foundries seems greatly exaggerated. The pure-play foundry market is projected to reach $29.6 billion in 2012, up 12% from 2011, according to IHS. This business will grow by 14% in 2013, with double-digit growth continuing in 2014 and 2015, they said.

20nm challenges
Still, the 20nm node represents a pivotal juncture. Intel has made the shift from conventional planar transistors at 32nm to 3D finFETs at 22nm. For foundries, 20nm represents the last node in the planar era, because planar is beginning to suffer from undesirable short-channel effects.

And previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process. “As we move to 20nm, the fundamental differentiation between high-performance and low-power processes is going away,” explained Mojy Chian, senior vice president of design enablement at GlobalFoundries.

This move, coupled by delays in past nodes, prompted some industry pundits to imply that the fabless-foundry model is somehow broken. Chian dismissed the notion, saying the “fabless-foundry business is thriving.”

So what will keep the fabless-foundry model viable? There must be more collaboration and a new mindset, in which the foundries must change from being mere manufacturing partners into virtual IDMs, Chian said. “New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the time-to-market,” he said.

Vendors must also make some tough choices. On the CMOS front, for example, the foundries will generally move to conventional bulk silicon at 20nm, due to cost. GlobalFoundries is in the bulk camp, but it will also make select chips for IBM and STMicroelectronics using fully depleted SOI (FD-SOI) at 28nm and 20nm.

Regarding SOI, Soitec is offering another CMOS technology option. It provides SOI for planar (FD-2D) and finFET (FD-3D) devices. FD-2D has 241 process steps, compared to 328 for bulk, according to Soitec. SOI wafers are more expensive, but IC makers can offset the costs with fewer process steps, more performance and less power, said Steve Longoria, senior vice president of strategic business development at Soitec.

Jeff Lewis, senior vice president of marketing and business development at SuVolta, said the industry needs a new solution besides bulk and SOI at 20nm. “The cost-per-transistor is higher at 28nm than 40nm/45nm,” Lewis said. “The problems get worse for the 20nm node due to double patterning.”

Another problem is transistor threshold voltage variation, which is caused by systematic and random variations, he said. A phenomenon called random dopant fluctuation (RDF) causes more than 70% of all random variations at 65nm and the problems are getting worse at each node. “In scaling, you start to get mismatches from one transistor to another,” Lewis said. “So the threshold voltages start to vary.”

To solve RDF and other problems, SuVolta recently rolled out a new transistor option that extends conventional bulk CMOS technology. SuVolta’s Deeply Depleted Channel (DDC) technology works by forming a deeply depleted channel when a voltage is applied to the gate.

Beyond 20nm
The problems continue to mount beyond 20nm. It’s unclear if EUV will be ready for the 14nm node. So, IC makers must contend with costly multi-pattering schemes. On the transistor front, Intel has made the migration to finFETs, but its technology has been a hot topic of discussion. Some “have painted Intel as being in trouble with tri-gate because images from a tear-down showed the fin was not squared off, but more shaped like a half-oval,” VLSI’s Hutcheson said.

Others have shown more vertical fins. “It’s very doubtful that Intel is in trouble,” Hutcheson said. “To get a squared off shape would be easy, but it adds steps, hurts yields, and dramatically increases cost.”

Intel may have made some tradeoffs to solve one bulk finFET challenge: height variation. In finFET production, there is an etch step, followed by a back-fill oxide process, and then an implant for junction isolation. The hard part is to make fins with consistent heights during the etch process.

Because of height variability, there are fears that the foundries could struggle making bulk finFETs with any consistency. In response, one foundry claims to have overcome some of these obstacles. According to a paper at the recent IEDM, GlobalFoundries implemented a dual shallow trench isolation (STI) process to ensure fin height control. Its high-k/metal-gate scheme also helped construct “tall/narrow” fins with less doping for better RDF, according to the paper.

FinFETs provide a 40% improvement in power reduction, but the technology still doesn’t put the cost-per-transistor back on the 29% reduction curve. “You are getting a significant power advantage,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “It’s still a challenge to translate that to a die cost reduction.”

All told, the industry should take a harder look at SOI, said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. “FD-SOI is a fairly simple process, but there is a cost penalty,” Patton said. “When you get to finFETs, it’s a different story. The cost issue becomes neutral between bulk and SOI. Variability is also an advantage for SOI for finFETs.”

In the SOI model, “you place your order to the substrate supplier,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that promotes SOI. “The height of the fin is pre-determined. It’s pre-made for you.”

Fin variability in bulk finFETs is about 140% to 170% higher, versus SOI finFETs, according to the SOI Consortium. In the front-end-of-the-line (FEOL) process alone, SOI finFETs have 56 process steps, compared to 91 for bulk finFETs, the group said. In total, the FEOL cost for SOI finFETs is $561, compared to $805 for bulk, they said.

Still, GlobalFoundries, TSMC and Samsung are banking on bulk finFETs at 14nm for two reasons. First, it’s unclear if the SOI wafer suppliers can meet demand during crunch times, said GlobalFoundries’ Kengeri. “Historically, customers are not used to designing in SOI. They are comfortable designing with bulk,” he said.

What’s next?
Beside traditional finFETs, there is also talk about a hybrid approach. In this concept, chip makers would combine finFETs and planar devices on the same chip. The planar devices could include analog IP. “This is not easy to do,” Kengeri said. “It’s a complicated process.”

A more likely scenario is that current finFET technology would be scaled at least two generations to 10nm, he said. Then, at 7nm or before, the industry is looking at various next-generation finFETs to solve the mobility problems. The candidates include quantum well finFETs, PMOS germanium finFETs, and SOI. “From a research point of view, we’re looking at everything, but nothing is settled,” Kengeri said.

By David Lammers

TSMC chairman and CEO Morris Chang said the early demand for mobile ICs at the 28nm node is behind a decision to increase capital expenditures for this year, including a pull in of construction of a 20nm R&D process line.

The $700 million pull-in plan for the 20nm R&D line will raise TSMC’s capital expenditure plan to the $8-8.5 billion range for this year, the beginning of what Chang said is likely to be several years of stronger investments. The new capex plan is a strong upward revision from the earlier plan to spend $6 billion for this year on capacity expansions.

On a conference call following release of the foundry’s first-quarter results, Chang was asked about the motivation for the earlier-than-expected construction of the 20nm R&D line. The 28nm node is the first technology generation in which mobile ICs played such a large role in the beginning phase of a process node, Chang said.

(Source: TSMC, April 26, 2012)

“The very big users (in the mobile space) have played a very big role in the 28nm ramp, and we have had to ramp 28nm production very fast, faster than ever before. In past nodes we did not have such big users pushing us to add capacity at the initial stages of a technology generation.”

Chang said the 20nm node may ramp “even faster than the 28nm node.” The early capex in the 20nm pilot line will allow TSMC to “shorten the learning cycle. We feel it is to our advantage to learn faster, sooner, and that is why we are pulling in the $700 million in capex,” Chang said.

Dotted Line Roadmap

While the TSMC executives said they are confident about strong demand, they acknowledged that the company’s technology roadmap remains in flux.

Chang was asked if TSMC will switch from a planar to a finFET technology at the 14nm node, or at a “later version” of the 20nm node. Chang said “at this point I am not going to commit or predict,” acknowledging that TSMC is considering pulling in finFETs prior to the 14nm node. Fabless companies have been pressuring their foundries to move quickly to the vertical transistors.

Another analyst asked if the foundry’s costs would increase sharply, with EUV, finFETs, and 450mm wafers all on the horizon, requiring a “sustained capital intensity” higher than in recent years. Chang said growth prospects for this year and the next few years are strong enough to bear the higher investments.

“I can’t answer you in a few sentences. We are having to integrate all of the financial factors into a business equation. Before we commit the kind of capital required, we must have the potential to get a good return on our investment. We must have a pretty good grasp on that before we commit the capital.”

But Chang said a capital intensity of  40-50 percent “doesn’t bother me,” noting that there have been previous periods of such strong investments when demand was strong, as it is now. “The years of 20-25 percent capital intensity have been low growth years,” he wryly added, saying that “it is a question of seizing a growth opportunity when it presents itself.”

The lithography conundrum needs to be resolved by the middle of 2013, he said. TSMC’s lithography supplier has been working “very actively” on both immersion 193nm and EUV technology, with plans to “increase immersion throughputs pretty dramatically.” While improvements to EUV throughputs have been notable over the last six months, EUV remains “pretty far” from the kind of throughputs that will make it production-worthy.

“Over the next 12-14 months, by the middle of 2013, we need to make quite a critical decision about which way to go: faster immersion, or faster EUV,” Chang said.

The TSMC founder said the 28nm node promises to be the strongest technology generation in the company’s history, surpassing the 65nm node, which had “mountain top” output of 120,000 to 130,000 wafers per month. “I expect the 28nm generation will top that,” Chang said, with the peak reached in 2014.

Asked about TSMC’s expectation for this year in the total number of 28nm processed wafers, chief financial officer Lora Ho said about 350,000 to 400,000 28nm wafers will be produced this year. Fab 15 will begin 28-nm volume production this month, and then ramp “at a fastest speed in our history” to reach ~50,000 wpm by year-end.

At the company’s Austin technology symposium, executives said TSMC is adding 28nm capacity at its gigafabs in Hsinchu (Fab 12) and Taichung, in central Taiwan (Fab 15). Rick Cassidy, president of TSMC North America, said demand for 28nm ICs includes smartphone processors, graphics, and FPGAs, among others. Cassidy said the 28nm capacity expansion at Fab 15 was pulled in by three months, and the capacity ramp is gated by how fast the company can install scanners and other key pieces of equipment.

“We are tapped out at all of our equipment suppliers,” Cassidy told the Austin audience.

Len Jelenik, a semiconductor manufacturing analyst at IHS, said he expects most of the major foundries to increase their capital expenditures this year.

UMC had a strategy of being a “fast follower” to TSMC, but then found that a major customer, Altera Corp., switched much of its production to TSMC in order to stay at the leading edge. That caused UMC to return to a strong focus on staying at the leading edge, Jelenik said.

SMIC also is likely to boost its capital expenditures this year, filling out empty shells in its China fabs.

GlobalFoundries will begin producing 28nm products late this year, starting with game ICs made for IBM on a foundry basis. Jelenik said GlobalFoundries also has room at its Malta shell to sharply increase production after the fab is up-and-running.