By Mark LaPedus
What impact will Intel have on the overall foundry business? In a research note, Weston Twigg, an analyst with Pacific Crest Securities, said: “Competition between Intel and the foundries, and the foundries and each other, should force high spending at the leading edge over the next two to three years. We remain bullish on equipment demand as long as Intel continues to play an aggressive role in the x86 versus ARM battle and its new foundry effort. We believe Intel is attempting to exploit its manufacturing technology advantage, which should pressure rivals TSMC and Samsung to maintain aggressive node transition plans.”

Staying in the leading-edge process technology race requires deep pockets. At 20nm and beyond, chipmakers will have to raise the CapEx ante to stay in the race. “Capital and production costs are rising faster than historic levels as logic and foundry producers migrate to 20nm and below,” Twigg said. “We expect equipment costs to rise 25% at the 22nm node and 28% at the 14nm node. New gate technologies, along with multiple-patterning steps and pitch-splitting techniques, are driving costs higher.”

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena—a series of events that brings the technology one step closer to mass production.

In coordination with the National Academy of Sciences, GlobalFoundries helped host a conference titled, “New York’s Nanotechnology Model: Building the Innovation Economy” at the Hudson Valley Community College in Troy, N.Y.

Fabless ASIC house Socle Technology named Michael Noonen as its new chairman. Noonen is still the executive vice president of global sales and marketing at GlobalFoundries, which is an investor in Socle.

The Silicon Integration Initiative (Si2) said that the ESD Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.

Mentor Graphics announced availability of a comprehensive IP-to-system, UPF-based low-power verification flow.

ARM and Cadence disclosed the details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16nm finFET process.

Peregrine Semiconductor said that its UltraCMOS phase locked loop (PLL) frequency synthesizer and prescaler devices are designed into six Globalstar mobile communication satellites that were launched into orbit in February. UltraCMOS is an advanced RF silicon-on-Insulator (SOI) process.

Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials, has been named a fellow of the Institute of Electrical and Electronics Engineers (IEEE).

Sematech executive Raj Jammy has joined Intermolecular as senior vice president and general manager of the semiconductor group.

RF Micro Devices announced the appointment of James Clifford, a former executive at Qualcomm, as vice president of foundry services.

More than one quarter of installed wafer capacity worldwide is dedicated to producing IC devices using process geometries smaller than 40nm, according to IC Insights.

In 2012, Intel retained the No. 1 market share position for the 21st year in a row, according to Gartner. Qualcomm climbed from No. 6 in 2011 to No. 3, and now trails only Intel and Samsung. Texas Instruments retained its fourth-place ranking, although Toshiba slipped to fifth place.

By Mark LaPedus

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena–a series of events that brings the technology one step closer to mass production.

On the 3D front, GlobalFoundries has produced its first functional 20nm silicon wafers with integrated through-silicon vias (TSVs). At its Fab 8 facility in Saratoga County, N.Y., the silicon foundry vendor manufactured TSV test wafers using its 20nm-LPM process technology.

At the same time, the company also demonstrated a 32mm x 26mm interposer test vehicle for 2.5D chips. For some time, it has been developing a 65nm interposer manufacturing line within its Fab 7 complex in Singapore.

These are key steps to enable the eventual production of 2.5D and 3D chips. GlobalFoundries’ next step is to work in conjunction with its chip-assembly partners. At some point in the future, the OSATs will take the TSV-enabled wafers and then assemble and qualify 3D test vehicles for customers.

GlobalFoundries is making progress on other fronts. It is taping out a 3D design for an undisclosed customer and is working with two others on 2.5D. “2.5D is already here,” said David McCann, vice president of packaging technology at GlobalFoundries.  “Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality.”

Other foundries, including IBM, Samsung, Tezzaron, TSMC and UMC, are also ramping up or developing their respective 2.5D/3D capabilities. But advanced chip stacking has several challenges and is still a few years away from mass production. Some estimate that volume production won’t occur until 2014 or 2015.

E. Jan Vardaman, president of TechSearch International, said the ability to obtain stacked memory is one of the stumbling blocks for 3D designs.  Devices based on the Wide I/O-2 standard are not due out until 2014 or 2015. “Everyone is waiting for the memory cubes,” Vardaman said. “The main question is when are the memory cubes going to ship?”

There are other issues as well. “I think that a number of people are trying out new materials to handle the bond/debond step. That takes more time,” she said. “Many companies indicated they still needed floor planning tools.”

Cost, of course, is still a factor. “Once the technology issues are resolved, the industry will need to bring up the yields in order to lower the cost,” she added.

Still, GlobalFoundries is moving full speed ahead in the arena. Last year, the company entered the 2.5D/3D chip-stacking foundry market and began to install the production tools within its Fab 8 complex.

Now, the company has developed the first 20nm silicon with TSVs, which measure 6u in diameter and 60u deep. “Our integration strategy works for TSV,” McCann said. It is also obtaining good results and yields with its silicon interposer technology in Singapore, he added.

GlobalFoundries’ strategy is far different than TSMC and Samsung, both of which are offering turnkey solutions. In contrast, GlobalFoundries will handle the traditional front-end steps and the “via creation” process. Then, the foundry vendor will hand off the traditional backend steps—such as temporary bonding/debonding, grinding, assembly and test—to the third-party packaging houses.

GlobalFoundries’ strategy, according to McCann, is more flexible and has more advantages over the turnkey model. “Our supply chain is an open model,” he said.

Like its rivals, GlobalFondries utilizes a “via-middle” approach to TSV integration. To overcome the challenges associated with the migration of TSV technology from 28nm to 20nm, the company has developed a proprietary contact protection scheme. This scheme enables the company to integrate the TSVs with minimal disruption to the 20nm-LPM platform technology, demonstrating SRAM functionality with critical device characteristics in line with those of standard 20nm-LPM silicon.

By Mark LaPedus
The first wave of 2.5D chips using silicon interposers are trickling out in the marketplace.
FPGA vendor Xilinx was the first chipmaker to ship a 2.5D device, and Altera, Cisco, Huawei and IBM recently have talked about their respective 2.5D chip developments.

Generally, Altera and Xilinx have taken a somewhat identical and straightforward approach. The two companies are separately developing 2.5D FPGAs, initially based more on homogenous devices. Both are also using Taiwan Semiconductor Manufacturing Co. Ltd.’s turnkey solution to integrate all or part of their 2.5D FPGAs.

Huawei is taking a different avenue, which is arguably more representative of the complex approach that many may take in their 2.5D efforts. The Chinese networking equipment giant is developing a heterogeneous 2.5D device that combines an FPGA from Altera and stacked DRAM from Tezzaron. The interposer comes from Singapore’s Institute of Microelectronics (IME). And fabless ASIC vendor eSilicon is handling the supply chain and integration process.

Putting the pieces together is expected to be a herculean effort. But having explored a multitude of options, Huawei decided to move down an arduous path—and for good reason. “The memory wall is a very serious problem,” said Anwar Mohammed, a senior staff scientist at Huawei. “The gap is becoming wider and wider. And all of the solutions we have for solving the problem are not working anymore.”

For the high-end networking space, Huawei sees a clear but challenging path to solve the problem. “We have to punch a tunnel through the memory wall,” Mohammed said. “For networking applications, 2.5D is the preferred solution.”

The roadblocks
The memory bottleneck and resistivity problems in planar devices have fueled the development of stacked 2.5D and 3D chips using through-silicon vias (TSVs), whether those TSVs run through a die or a separate interposer die in 2.5D designs.

Mike Splinter, chairman and chief executive of Applied Materials, said the 2.5D/3D chip market represents a promising segment for the IC industry, but the business will take some time before it reaches mass production. “We’ve always said there will be a slow deployment of 2.5D,” Splinter said.

The 2.5D chip market is progressing somewhat faster than 3D. Several foundries and IC-packaging houses currently provide interposers and workable manufacturing flows to enable 2.5D designs. There are still some gaps in the technology, however.

“2.5D depends on having a stacked memory solution,” said E. Jan Vardaman, president of TechSearch International, a research firm. “The inability to obtain a memory stack is a gating factor. Some people also say the cost for 2.5D is too expensive.”

Test is also an important but sometimes overlooked part of the flow. “The test challenges for 2.5D are very similar to 3D. For die stacking, it is crucial to have each die pre-tested for KGD,” said Bassilios Petrakis, product marketing director at Cadence Design Systems.

“In the case of the interposer, the question often comes up as to whether it needs to be tested for connectivity upfront prior to bonding with other dies. There is also consideration for how to test partially populated interposers as well as multiple die stacks,” Petrakis said. “An example of that would be a logic die that talks to a Wide I/O DRAM and another logic die on top. If the bottom die of the interposer is the most expensive die, you may only want to attach it to an interposer with all other die attached that have been tested good so far. This may be the most economical way to produce good modules. Finally, all dies on interposers must have some form of a wrapper with boundary scan. We prefer the use of IEEE 1500-style wrappers, but we are also able to accommodate the simpler Wide I/O style boundary scan. Special I/O wrap test before die stacking/bounding can detect possible TSV shorts but not opens.”

Another challenge is to find a suitable manufacturing partner. In general, there are two schools of thought—turnkey versus a hybrid approach. TSMC and Samsung provide a turnkey solution, in which the companies provide both the front- and back-end work. In contrast, GlobalFoundries and UMC are sticking with their hybrid approaches. In that model, the foundries handle the front-end steps, but pass on the back-end work to the IC packaging houses.

Both approaches have their advantages and disadvantages. In the turnkey approach, the foundry can assume the responsibility of the supply chain, thereby keeping costs and quality under strict control. The problem with the turnkey method is that some customers are nervous about handing over their sensitive front-end, assembly and test intellectual-property (IP) to a foundry, said Ajit Manocha, chief executive of GlobalFoundries. “We are not a closed fab,” Manocha said. “Customers prefer to take their proprietary information to the OSATS. We are not going to force customers to do the assembly with us.”

Taking the right path
As it turns out, each customer will choose its own path. To simplify its respective supply chains, Altera and Xilinx are working with a limited set of partners. Most others may end up dealing with a more complex supply chain.

Huawei, for example, is working with separate chipmakers, interposer suppliers, foundries, assembly houses and integrators. At present, Huawei is developing its 2.5D ASIC/FPGA device at IME, a Singapore R&D organization. IME has set up a complete front-end production flow using fab gear from Applied Materials. IME also developed its own interposer technology. IME is a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR).

Huawei declined to comment on which foundry it will use once it moves into production, but the challenges are obvious. “This could be a logistics nightmare,” said Ron Leckie, president of Infrastructure Advisors, a consulting firm.

Unfazed by the challenges, Huawei believes it must move in a new and radical direction to address the memory bottleneck in the network. “At one time, when you went to a new node, your gains were pretty sharp,” said Huawei’s Mohammed. “Now, every time we go to the next node, the power becomes a challenge and you have to go with larger and larger die sizes.”

The current line of specialized networking memory chips and other components are unable to keep pace. “Commodity memory cannot handle it,” he said. “Serdes was able to help with the bandwidth at one time. But now, the gains are flatter.”

To solve the problem, the company evaluated several options. “A company like Huawei doesn’t jump into a technology. We have to go through many doors before we decide this is a technology we go after,” he said.

Last year, for example, Huawei looked at combining an ASIC and RLDRAMs in a 64mm x 64mm package, he said. After dropping that idea, the company looked at integrating those devices in larger substrates or smaller packages. Those options were scrapped. Then, it looked at combining a bare die FPGA and packaged memory in a $25 module. “It was not leading-edge technology,” he said. “Any one of our competitors could have picked it up.”

Finally, the company decided on 2.5D. 3D is more suited for mobile applications. “The size of our line cards is constant. We want to put more and more items on the line card to make it more functional and effective. 2.5D is a very powerful enabler for that,” he said. “Initially, this is going to be more expensive. But if you combined enough items, there is a strong potential for cost reduction. It also allows us a faster time to market.”

In Huawei’s proposed design, the FPGA from Altera and the memory stack from Tezzaron are situated on a silicon interposer. “Instead of 10 or 20 DDR DRAMs, all of this can be replaced by one Wide IO memory,” he said. “DDR memory performance is so slow. All of this goes away with Wide IO memory, which is only 12mm x 12mm.”

In total, the company’s proposed 2.5D device occupies less space. The bandwidth per watt is at least 30 times better than conventional approaches, he said.

To realize its design, the world’s largest networking equipment company must overcome some major hurdles, namely the KGD issues, the lack of EDA tools and the supply chain. “Hopefully, we can obtain known good dies and bare dies,” he said. “There is good work going on at Cadence, Mentor and others, but this is still an area of concern. There are also some business concerns like who’s responsible and who’s not responsible?”

Ultimately, to make 2.5D/3D a viable solution in the overall market, Huawei advocates another critical piece to the puzzle–collaboration. “We are advocating pre-competitive collaboration. Let’s makes sure the technology succeeds. When the technology can take care of itself, let’s start competing,” he added.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss IC packaging trends with Rich Rice, senior vice president for North America at Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest independent IC packaging and test house.

SMD: Amazingly, there are still more than 100 vendors competing in the IC test and assembly business today. But for years, we’ve been waiting for a major shakeout in the sector. When will we see the shakeout?
Rice: It will eventually happen. It’s hard to say when this will take place. In packaging, the top subcontractors are fairly broad-based in the markets they serve. There are only so many companies in this space. Meanwhile, the smaller subcontractors generally offer niche technologies. But some of smaller subcontractors have specialized tooling and unique packaging. That type of thing is difficult to replicate, especially when the cost is very low and there is fully depreciated equipment involved. Those things tend to keep the smaller subcontractors in place for a long time.

SMD: Where are we in the business cycle in IC packaging?
Rice: In packaging, I wouldn’t say business is slow, but it’s not strong. As you know, the global semiconductor market has been somewhat tepid. The products that are selling in the market are the iPhone, iPad, Samsung Galaxy and things like that. If you are designed into one of those products, you are doing okay. If you are not, you are probably struggling.

SMD: Where are we in 3D TSV technology?
Rice: A lot of the fundamental assembly and interposer work is progressing. There are still challenges. Yields are definitely going to be a challenge. The question is how you manage yields. Then, you have test challenges. I personally feel pretty comfortable about the progress on that front. Overall, 3D TSV technology is not ready for high-volume production. Memory seems to be a limiting factor. The memory availability on these larger stacks is going to define when these 3D products will get launched.

SMD: When will we see stacked die in mobile phones?
Rice: In mobile, we’d love to have 3D. But it’s not going to be ready for a while, probably because of memory stack availability. Plus, the big OEMs hold a lot of the cards on when 3D might potentially be used and deployed.

SMD: For some time, ASE has talked about providing silicon interposers and 3D technology. What is the latest at ASE?
Rice: We have an interposer technology that we’ve promoted. We are not sure what the market acceptance is. Poking holes in silicon is mostly a foundry business. We can do some of it. We can do very simple dry etch processes on a die, via last and very course technologies. But for really fine-pitch 3D ICs or 2.5D interposers, that’s really a foundry type of business.

SMD: So ultimately, what role will OSATs play in the 2.5D and 3D market?
Rice: We will do the backend integration processes.

SMD: As you know, TSMC is offering a turnkey solution in 2.5D/3D. How do you see that playing out?
Rice: The guy that does the integrated solution will probably end up with a low mix, meaning a smaller number of device types, but probably at high volumes. My rationale behind that is very simple. Foundries have a common process platform. They are not tweaking their processes a lot. In other words, they have a lot of different devices that go through the same process.

SMD: What challenges will TSMC face doing the backend processes?
Rice: They must deal with having a toolbox with various interconnect technologies, and how you put it together, and how you manage that. It’s something we do day in and day out. And they don’t.

SMD: There is still a lot of activity in traditional packaging. What are some of the trends at the high end?
Rice: There are different markets. The advanced wafer node market has been driven by PCs, graphics, CPUs as well as servers. Typically, you will see larger packages with a ton of pins. For example, you have flip-chip BGA. We’re talking about pin counts in the thousands. This is where you will see the eventual introduction of 2.5D interposers.

SMD: What about other packaging markets?
Rice: On the cost-performance side, we look at this as the consumer market. In this market you have simple wirebond BGA and QFN. QFN is an industry word for quad-flat no-leads. The leads are basically on the bottom of the package. On the systems integration front, this is where you start seeing a lot of multi-die integration. For instance, you have PoP, or package-on-package. In PoP, you have a logic processor on the bottom and a memory on top. In PoP, we are seeing anywhere from 500 to over 1,000 pins. These are typically for mobile devices.

SMD: Where is PoP heading?
Rice: PoP morphs into different approaches as we try to make it thinner. We want to keep that down to 1mm or lower. While we are trying to make it thinner, we are also doing embedded technologies. You might embed a passive or active in the actual substrate itself. You might put capacitors as close as possible to the I/O of the die. You might embed a simple active component such as a power management device. You may want to embed components close to the processor, which can help with the power control and supply. In embedded PoP, you’re trying to get as much silicon packed in a particular volumetric area on the package.

SMD: What are the challenges with embedded PoP?
Rice: It’s disrupts the supply chain on how substrates are made. The substrate suppliers have not had that kind of capability yet, such as handling bare die or handling passive components inside their lines. In addition, if the interconnect is not robust or the yield is bad on the silicon, you throw away the whole substrate.

SMD: Is the embedded PoP shipping now?
Rice: Probably soon.

SMD: Another next-generation PoP is fan-out. Where is fan-out going?
Rice: In fan-out, you could make a really thin package. If you can get your signals from the bottom to the top of the package, and then put another memory package on top, you can get a fairly thin solution. It’s on our roadmap. We’ve had a fan-out production line for a long time. We were one of Infineon’s early fan-out licensees. We’re manufacturing on a 200mm format. To go to 300mm is a large investment. STATS ChipPAC has 300mm capability. We choose not to chase 300mm at this time.

SMD: What are the challenges with fan-out?
Rice: In terms of making holes through that package, we found it to be quite difficult. It’s a different type of mold compound. You have to use alternative means to get the signals up to the top. Secondly, as far as the package infrastructure itself, it is a wafer-level package. Wafer-level package infrastructure is quite different than regular package infrastructure. The investment level is much higher. So, you have to calculate your payback.

SMD: Is that why ASE is pursuing embedded PoP?
Rice: Potentially, you can embed a die into a PCB in a panel format. That could be more cost-effective than using a wafer format. It’s a lower cost infrastructure.

SMD: What else is going on in packaging in mobile phones?
Rice: With mobile phones, the board technology is extremely dense. The PCB is a high-density, built-up substrate. It can also handle very fine-pitch interconnect. You are also placing wafer-level CSPs on top of the substrate, which are essentially bare die. So, the mobile phone platform is essentially becoming a big package. Your cell-phone motherboard, in a sense, is a multi-chip module.

SMD: Is that driving the demand for wafer-level CSPs?
Rice: In most cell phones, a very high percentage of the components now are wafer-level CSPs. These components used to be housed in packages like BGA, QFP or QFN. Now, they are moving towards wafer-level CSPs, which are mounted to the motherboard. That’s why you’re seeing the wafer-level CSP growth rate going so high.

SMD: Will the cell-phone PCB ultimately become the package?
Rice: If you look at all of these bare pieces of silicon that are going on the mobile phone motherboard, it’s almost like a big package. But I don’t see it all becoming one big package for a while. There is not a single chip that does everything in a phone. There are far too many diverse technologies, features and IP in a cell phone. For example, you will continue to see discrete application processor packages.

SMD: What else is going on in multi-die packaging?
Rice: The industry has shipped multi-die packages for decades. In an early and simple configuration, you saw two die in a PDIP or even two die in a transistor package. We are doing a lot of multi-die packaging today. We are literally doing hundreds of millions of units per month. Today, we see high-density, flip-chip being used with a wirebond part stacked on top of it. It is all molded into one package. We see a lot of wirebonding packaging, where you have a lot of multi-die in the package. There are a lot of die-to-die wirebonds. So, you get into some exotic layouts in how you do your wirebonding.

SMD: So where is IC packaging headed?
Rice: The packaging portfolio will continue to expand. We will see more packaging technologies that are different and unique.

By Mark LaPedus

GlobalFoundries’ recent move to announce a new R&D center will accelerate its efforts to bring technologies from the lab to the fab. And the R&D facility will speed up the foundry company’s efforts to develop its 10nm and 7nm processes, according to Ajit Manocha, chief executive of GlobalFoundries, at an event.

At the same event, Manocha also dismissed reports that the silicon foundry vendor will shortly announce a new fab. “We are not announcing another fab,” he said.

Last week, the company did announce plans to build a multi-billion dollar R&D facility at its Fab 8 campus in Saratoga County, N.Y. Representing an investment of nearly $2 billion, the new Technology Development Center (TDC) is expected to play a key role in the development of next-generation process technology, 2.5D/3D packaging, lithography and photomasks.

The TDC will “accelerate our ramp to 10nm and 7nm,”  Manocha said during a keynote at the Industry Strategy Symposium (ISS) on Monday (Jan. 14). The ISS is sponsored by SEMI.  “The $2 billion investment (will) help close the gap between the lab and fab.”

The keynote was entitled, “Reshaping the Foundry Industry: Welcome to Foundry 2.0.” In the new model, there is a deeper and earlier collaboration between foundries and their customers. The collaboration, coupled with the new R&D center, enables GlobalFoundries to realize the “virtual IDM model,” he said.

The industry must collaborate more amid the shift towards new and complex process nodes. In September, GlobalFoundries rolled out its finFET technology for the 14nm node. GlobalFoundries is taking a “modular fin” approach with its bulk finFET offering, dubbed 14nm-XM.

By taking the modular approach, the company has accelerated its process roadmap by a year. Production, which is slated for 2014, will take place within GlobalFoundries’ new 300mm fab in New York.

The foundry vendor plans to move into production with its 10nm finFET process in 2015, a year after its 14nm finFET technology ramp. GlobalFoundries plans to make an announcement regarding the 10nm technology this year, Manocha said.

Then, in 2017, the company plans to roll out its 7nm technology. To help those efforts, it plans to build the new R&D center. The TDC will feature more than a half million square feet of space, which includes a cleanroom and a laboratory. The facility will increase the total capital investment for the Fab 8 campus to more than $8 billion. Construction of the TDC is planned to begin in early 2013, with completion targeted for late 2014.

The TDC will house a variety of semiconductor development and manufacturing spaces to support the transition to new technology nodes. It will provide a collaborative space for the company to devise new interconnect and packaging technologies, photomasks, and lithography technologies like extreme ultraviolet (EUV).

Since breaking ground on Fab 8 in 2009, the foundry vendor has created approximately 2,000 new direct jobs and that number is expected to grow by another 1,000 employees for a total of about 3,000 new jobs by the end of 2014.

By Mark LaPedus
Over the last year, leading-edge silicon foundries announced their new and respective strategies in the emerging 2.5D/3D chip arena. The ink is barely dry and now the foundry landscape is changing.

One new vendor, Tezzaron Semiconductor, is entering the market. The 3D DRAM supplier plans to provide select 2.5D/3D foundry services within its recently acquired fab in Austin, Texas.

In addition, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is tweaking its 2.5D/3D foundry strategy. Last year, TSMC announced a controversial turnkey solution. The company not only provides the front-end steps, but also the back-end work traditionally handled by the IC packaging houses. Now, instead of locking in customers with its front-to-back solution, TSMC is rethinking its position.

“We prefer to do it ourselves,” said Morris Chang, chairman and chief executive of TSMC, in a recent conference call. “We have become more flexible to partner with the OSATs.”

Two other vendors, GlobalFoundries and UMC, are sticking with their collaborative approaches. In that model, the foundries handle the front-end steps, but pass on the back-end work to the IC packaging houses.

Another foundry, IBM, has a slightly different strategy. Still to be seen, however, is what Intel and Samsung will do in the arena. And some of the IC packaging houses have given up the notion of doing fine-pitch interposers and through-silicon vias (TSVs). Instead, the OSATs are looking at doing course-pitch TSVs and interposers.

So, in general, there are two prevailing, leading-edge 2.5D/3D foundry models: TSMC’s turnkey solution and the rival collaborative approach. “I think both models will co-exist,” said David McCann, senior director of technical business operations for packaging and central engineering at GlobalFoundries.

Foundries go 3D
The memory bandwidth gap and resistivity problems in planar devices have fueled the development of 2.5D/3D chips. But advanced chip stacking has several challenges and is still a few years away from mass production. For example, TSMC will not see “significant revenue” in 2.5D/3D until 2015 or 2016, Chang said.

2.5D/3D technology and the associated supply chain are immature. Manufacturing costs are falling, but there is still a perception that the 3D devices will be prohibitively expensive, said Niranjan Kumar, product marketing manager for TSV programs at Applied Materials.

So far, only a few chipmakers have announced 3D chips. In 2010, Samsung rolled out one of the first 3D DRAMs using a 40nm process and TSVs. Then, last year, Samsung and Micron formed a consortium to develop a serial specification for a 3D DRAM technology called the Hybrid Memory Cube (HMC). Micron will sample HMC devices in 2013. Aimed at high-end applications, HMC will stack DRAM arrays on a logic chip. IBM is making the logic chip based on an SOI substrate.

Another 3D DRAM vendor, Tezzaron, recently has begun shipping its initial parts. But other 3D DRAM schemes, such as Wide I/O, have been delayed due to an assortment of technical issues. Still, the industry is making more progress on the 2.5D front. “The 2.5D era has arrived,” said E. Jan Vardaman, president of TechSearch International, a research firm.

To date, Altera, Cisco, IBM, Huawei and Xilinx have talked about or shipped 2.5D devices using interposers. In fact, Xilinx has shipped the Virtex-7 2000T FPGA, a product based on a 28nm process and a 65nm silicon interposer.

The device itself is built and assembled by TSMC, which refers to its 2.5D/3D turnkey solution as “Chip on Wafer on Substrate” (CoWoS). Using CoWoS, TSMC is also building a rival 2.5D FPGA for Altera. In CoWoS, the chip is attached to the substrate to form the final component. TSMC provides front-end manufacturing, TSV formation, interposers, chip-on wafer bonding, backside thinning, dicing and final test.

CoWoS has been given a lukewarm reception by the IC packaging houses, many of which believe that TSMC is taking a chunk of the backend business away from the OSATs. “For some customers, (CoWoS) works well. It doesn’t work for all customers,” Vardaman said.

TSMC has defended CoWoS, saying that the in-house, turnkey solution enables the foundry to ensure the quality of the chips and the production process. TSMC also assumes responsibility for the supply chain. “Technically, it is progressing well,” TSMC’s Chang said. “We are trying to reduce the costs.”

Beyond 2.5D FPGAs, TSMC recently taped out a Wide I/O device. To enable Wide I/O, the company requires DRAM from a third party. Originally, it was working with Elpida, which is being acquired by Micron. Now, TSMC is working with Micron and SK Hynix.

TSMC’s model may fall flat when customers ask for DRAM from Samsung. TSMC and Samsung are foundry competitors. It’s unlikely that Samsung will hand over DRAM wafers, along with its proprietary IP and test data to TSMC.

In some cases, it makes more sense to follow the collaborative model, where there are fewer conflicts. A customer can use its own logic and/or memory or buy it from a third party. The foundries do the front-end processing, while the OSATs collect and assemble the pieces.

With that scenario in mind, TSMC is warming up to the idea of working with OSATs to give customers more flexibility. TSMC also may be fending off its rivals, which are offering a collaborative approach.

More models

Others are moving full speed ahead with their strategies. Earlier this year, GlobalFoundries installed the tools to create 3D TSV devices on its 20nm platform within its fab in New York. It will handle the “via creation” steps. Then, it will hand off the traditional backend steps, such as temporary bonding/debonding, grinding and test, to the OSATs.

The foundry vendor also devised a low-volume, 2.5D line using 65nm interposers within its fab in Singapore. GlobalFoundries’ challenge is to demonstrate a smooth flow and good product yields at a competitive cost. “It’s going well,” said GlobalFoundries’ McCann. “The question is, can we make this collaborative supply chain model a one-to-one solution? We have to prove this to our customers.”

Another vendor, IBM, has been working on 2.5D/3D for years, including a specialized interposer technology. “IBM is working with Sematech to connect analog converter functions in a logic device with an interleaver IC in IBM’s BiCMOS SiGe technology,” said TechSearch’s Vardeman. “Applications are fiber optic telecom, high-performance RF, test equipment and processing for radar systems.”

The new kid on the foundry block is Tezzaron. In October, the company acquired the former SVTC fab in Austin. R&D foundry SVTC, which recently went bankrupt, originally acquired the fab from Sematech. Now, the fab operates under the name of Novati Technologies. Tezzaron is the sole shareholder in Novati. “We are going to become a 3D foundry,” said Robert Patti, chief technology officer at Tezzaron. “What we are trying to do is provide an open platform for 2.5D and 3D integration.”

Asked if Novati will compete against TSMC and GlobalFoundries, Patti said Novati can work with other foundries and will not compete against them. Novati will continue to serve SVTC’s customers. The Austin fab is a 200mm CMOS line, with 200mm/300mm backend capabilities.

As part of the plan, Tezzaron will shut down its current fab in Singapore and transfer the tools to the Austin fab by early 2013. By Q3 of next year, the company hopes to provide 3,000 wafer starts a week in Austin.

In the 2.5D/3D foundry arena, Novati will offer advanced stacking capabilities, TSVs and interposers. It can provide Tezzaron’s 3D DRAMs or procure third-party logic and memory chips. And Novati will offer both a turnkey and collaborative model. “We are willing to do a full turnkey solution,” Patti said. “I am willing to take the pieces and assemble them.”

The company prefers customers to use its so-called FaStack technology, which makes use of a proprietary bonding and tungsten process. Its 2.5D/3D technology is based on a 40nm process. By late 2013, it will offer a 28nm platform.

While the foundry landscape continues to evolve, several IC packaging houses are rethinking their plans. Some time ago, Taiwan’s Advanced Semiconductor Engineering (ASE) was looking at fine-pitch interposers and TSVs in a “via-last” production flow. “We have an interposer technology that we’ve promoted,” said Rich Rice, senior vice president of sales for North America at ASE. “We are not sure about the market acceptance.”

As it turns out, ASE discovered that leading-edge TSV and interposer work belongs in the foundries and not at the OSATs. “I think poking holes in silicon is mostly a foundry business,” he said at a recent event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

On the other hand, ASE and STATS are looking at course-pitch interposers and TSVs for niche applications like MEMS and RF. The OSATs will also play a major role in fine-pitch 2.5D/3D by offering the critical backend work.

TSMC and its turnkey model will not take all of the backend business away from the OSATs. TSMC is still going up the learning curve in the backend and may find the work a headache in the long run. “This is something we do day in and day out,” Rice added.

By Mark LaPedus
Advanced 2.5D/3D chip stacking has a number of challenges and is still a few years away from mass production.

In fact, mass production may not occur until 2015 or 2016. But OEMs can ill afford to sit still and wait for 2.5D/3D technology to mature. So, until 2.5D/3D is ready for prime time, chipmakers and IC-packaging houses are under pressure to innovate and extend current 2D-based technology.

Needless to say, OEMs demand smaller and lower power chips housed in thinner packages. “The silicon is getting more dense. There are also more I/Os on the chip. Packaging is becoming the burden,” said Raj Pendse, vice president and chief marketing officer at STATS ChipPAC.

In fact, IC-packaging houses currently are developing a dizzying array of new package types that promise to extend 2D technology. For example, the subcontractors are working on new packages that could evolve or replace the mainstream mobile technology: package-on-package (PoP). The next-generation PoP candidates include bond via array, embedded PoP, fan-in, fan-out, flip-chip PoP, and even multi-chip modules (MCMs).

“The mobile phone platform is essentially becoming one big package,” said Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE). “Your cell phone motherboard, in a sense, is becoming a multi-chip module.”

Surprise package
For decades, IC packaging mainly involved low-tech, labor-intensive work with a plethora of simple package types, such as DIPs, PGAs, PLCCs and QFPs. “Packaging used to be an afterthought,” said STATS ChipPAC’s Pendse. “Silicon was once the solution. The main goal of packaging was to encase the silicon so it wouldn’t fall apart.”

In the 1980s and 1990s, the world changed with the emergence of new consumer electronic items and the PC. IC packaging still remained in the shadows despite various innovations like BGA, CSP and flip-chip. More recently, there has been a sea of change in the industry. Chip complexity is increasing, but the geometries are shrinking. The boom in mobile is driving the need for new and thinner packages.

For example, there is a pressing need for a thinner PoP. Introduced several years ago for the mobile space, PoP is used for devices like ASICs, baseband chips and application processors. PoP combines separate logic and memory packages, which are stacked on top of each other. The bottom package is logic and the top is memory. The maximum height of the PoP packages is typically 1.4mm to 1.6mm, but the eventual goal is to drive the dimensions down to 1mm and below.

There are other design considerations. At the 65nm node, a processor had some 400 I/Os and consumed 400mW of power on a die size of 64mm-square, according to a recent presentation from DfR Solutions. But at 28nm, a processor has some 800 I/Os and consumes 1.2 Watts of power on a die size of 50mm-square, according to the firm.

Still, in next-generation mobile designs, the industry may need to shrink the PoP to 0.4mm. One way to boost PoP densities is a technology called fine-pitch copper pillar flip-chip packaging. “Copper pillar can help enable a smaller form factor for the bottom package,” said E. Jan Vardaman, president of TechSearch International, a research firm.

Copper pillar is not a packaging type per se, but it is a manufacturing technique to enable next-generation CSPs, PoPs and even 2.5D/3D chips. The technology moved into the limelight in 2010, when Texas Instruments and Amkor jointly rolled out copper pillar capabilities.

At the time, TI said that traditional wire-bonding technology would hit the wall at the 40nm node, thereby requiring copper-pillar flip-chip. In flip-chip, a device is mounted on a substrate face down. Traditional solder-based flip-chip is limited to 150um pitches. In copper-pillar, however, the pitches can be extended down to 50um in-line and 40um/80um staggered, according to Amkor.

In PoP, the top and bottom chips could be individually packaged using wire bonders. In another configuration, the top package could be wire-bonded, while the bottom package could implement copper-pillar flip-chip. Using copper pillar for the bottom package, PoP may be more expensive, but it enables higher I/O densities and increased thermal conductivity.

Flip-chip took several years to gain traction, but it is widely used for processors and graphics chips today. The lowly wire-bonder continues to have legs, as some 80% of the world’s chips are still assembled using wire-bonding techniques, according to Vardaman. “Wire-bonding will be around for a long, long time,” she said during a recent presentation at an event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

For years, the lead wires in wire bonding were based primarily on gold. Gold prices have skyrocketed in recent years, prompting many chipmakers to move to cheaper copper wiring. “Three years ago, the industry said wire bonding would not extend past 40nm,” said Y.S Kim, vice president of engineering at Signetics, an IC packaging house. “We are now qualifying copper wire bonding at 32nm.”

Signetics is also doubling its capacity for flip-chip package assembly within its factory in Paju, South Korea. The company offers standard bumping and copper-pillar flip-chip. The technology is being driven by finer-pitch packages in HDTVs, SSDs and smartphones.

Time for another PoP?
Besides flip-chip PoP, there are other next-generation PoP candidates, such as embedded wafer level ball grid array (eWLB). In typical wafer-level packages, the process steps are performed on the wafer and the interconnects are fit on the chip in a fan-in design. In eWLB, the interconnects are positioned in an arbitrary distance in a fan-out design. Unlike fan-in, eWLB’s package size and I/O count are not limited by the die size.

Infineon, STATS ChipPAC and others are pushing eWLB. With fan out, STATS ChipPAC can reduce the bottom PoP package in height to less than 0.5mm. Using fan out, the total height for a five-die package is less than 1mm. STATS ChipPAC is shipping multi-die versions of fan out packages in a 300mm manufacturing process.

The next step is to bring eWLB into the 2.5D/3D era. With the technology, STATS ChipPAC can embed multiple active and passive components in the same wafer-level package with a vertical 3D interconnection that can be achieved without the use of a TSV. “It is positioned for 2.5D integration. It’s an alternative (to 3D TSV),” said STATS ChipPAC’s Pendse.

Rival ASE is moving in a slightly different direction. Like STATS ChipPAC, ASE was an early licensee of eWLB from Infineon. Fan out requires a different tool and materials infrastructure. “The investment level is much higher,” said ASE’s Rice. “We are manufacturing it on 200mm. For 300mm, we chose not to do it.”

ASE and others are pursuing so-called embedded PoP. In embedded PoP, the die is embedded in the substrate in the bottom of the package. “You may embed a passive or active component in the substrate itself,” Rice said.

The idea is to embed components, such as the capacitors or power management devices, close to the I/O of the processor die. Embedded PoP could reduce the space and power consumption in mobile devices. It also has many of the challenges associated with MCMs. Embedded PoP may require bare die, which is difficult to handle and test. “It disrupts the supply chain on how substrates are made,” he said.

Embedding die into laminated substrates has been in development for years. For example, TI recently rolled out MicroSiP, a miniaturized system-in-package (SiP). MicroSiP is not a PoP package. Instead, it integrates ICs with passive components in a BGA format. The passives are arranged on the top, while BGA balls are arrayed on the bottom.

Then, a separate package, dubbed PicoStar, is embedded in the laminate substrate. All told, the combined MicroSiP/PicoStar package integrates a DC-to-DC converter with inductors and capacitors to provide a stand-alone power supply, said David Heacock, senior vice president of Silicon Valley Analog at TI.

In another PoP effort, Invensas, a subsidiary of Tessera, recently unveiled bond via array (BVA) technology. BVA PoP is a packaging alternative to Wide I/O. It has demonstrated scalability to a 0.2mm pitch and up to 1,400 I/Os. “BVA significantly pushes out the need for 3D TSV. At the same time, it renders solder via obsolete as it is able to cost-effectively scale to ultra-high I/O,” said Simon McElrea, president of Invensas.

Clearly, there are new PoP solutions waiting in the wings. OEMs will need to take a hard look at the new technologies and for good reason: 2.5D/3D technology is still not ready for prime time. “For 2.5D, 2014 will be a very interesting year. By the end of 2013, the capability will be in place. 3D mainly depends on memory standards and memory adoption,” said Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries.

Steve Pateras, product marketing director at Mentor Graphics, added: “From a tapeout point of view, 2.5D is happening this year. We have customers taping out 2.5D. For 3D, we’re seeing design activity for memory on logic. Next year we’ll see some tapeouts. There is no real activity in logic on logic yet.”

In any case, the role of packaging is changing. Packaging is no longer an afterthought. It is becoming an important part of the IC design and manufacturing process. “Today, it is an important part of the solution,” STATS ChipPAC’s Pendse said.

By Mark LaPedus
Semiconductor Manufacturing and; Design sat down to discuss the 3D device challenges and applications with Peter Ramm, head of the department for device and 3D integration at Fraunhofer EMFT Munich, one of Europe’s largest research organizations.

SMD: Fraunhofer was a pioneer in 3D chip R&D, right?
Ramm: We are the oldest microelectronics institute in Germany. We started in the mid-1980s with a big project in 3D. We were one of the first to work on this after NEC, IBM and others. We started with a 3D integrated circuit. We made an NMOS and PMOS layer. We made a second layer. We made vias through the layers at 2 microns. At the end of the 1980s, we realized a CMOS ring oscillator that was 3D integrated. But we were much too early with 3D IC integration. There was no real application division of a company that said: ‘Yes, this is exactly what we need for a product.’ So, we started looking at lower integration densities. The next project for us was in the direction of less vertical integration density using more smart technology.

SMD: What are some of the projects you are working on?
Ramm: We are working on interposers. We don’t like the term 2.5D. In fact, what they today call an interposer was called an MCM several years ago. MCMs existed some 15 years ago, but it was not a success story. So, no one is talking about MCMs. Now, the industry is talking about interposers. The disadvantage of the interposer is that it’s expensive. It’s not a cheap kind of 3D integration. You have to deal with thin silicon. You have to do a redistribution layer.

SMD: So what’s the solution?
Ramm: We are working on a thick interposer technology with Siemens. This is a stable substrate. The only problem is that the pitch is normally large. We are also working on a technology based on photo-assisted etching. With that, you can have diameters of the TSVs in the range of down to 2 or even 1 micron. So, you can have a thick wafer or substrate with a low pitch. You can metalize it with alloys.

SMD: What are the applications for this?
Ramm: This would be an alternative for a thin interposer. You can use it for anything. It could be a memory stack on a processor and so on. In this project with Siemens, the application is for MEMS-ASIC integration. A typical example is that you can have two ASICs. You have an RF receiver/transmitter and you have a controller. You can integrate them with an interposer and add a MEMS device. For example, you could end up with a pressure sensor.

SMD: What’s the status of this device?
Ramm: This is still in research and development.

SMD: What are the advantages of a thick interposer?
Ramm: The handling is easier, so it’s more cost-effective in fabrication. It’s like a standard wafer. For example, the thickness is 700 microns. You can, of course, make it thinner, as long as it stable.

SMD: Fraunhofer is part of the Best-Reliable Intelligent Ambient Nanosensor Systems, or e-BRAINS, project. What is that project?
Ramm: The e-BRAINS project is involved in the research and development for the integration of heterogeneous systems and ambient assisted living. So in fact, it’s about the combination of sensors and MEMS with ICs for the application of ambient assisted living. A part of this is 3D integration. There are not so many vertical interconnects in these types of systems. In this case, it can be hundreds or thousands of interconnects. The direction for us is in miniaturization. The task is to use 3D when it is needed. Typically, it’s not performance driven. It’s form- factor driven.

SMD: When did the e-BRAINS project start? Who are the partners in the group?
Ramm: It started in September 2010. It will end in September 2013. We have around 20 partners. The partners are Siemens, Infineon, SensoNor, Sorin, IQE, 3D Plus, DMCE, Vermon, Magna Diagnostics, EESY-ID, Fraunhofer, SINTEF, IMEC, CEA, EPFL, Tyndall, Technische Universität Chemnitz, ITE and TU Graz.

SMD: What is the goal?
Ramm: The demonstration vehicles will be in the areas of medical applications, such as a smart biosensor grain. In effect, it’s a DNA sensor. We are also looking at infrared imagers and active medical implants like pacemakers. For Siemens, we are looking at air quality systems for the applications in the home. It’s also interesting for applications in cars. The fifth application is smart ultrasound imaging for medical applications.

SMD: The e-BRAINS project is just a part of your 3D R&D activities, right?
Ramm: This is a part of our 3D activities. But looking into the future, I see it as a more and more important part.

SMD: What are some of the challenges?
Ramm: In the case of a pacemaker, it’s really miniaturization. The 3D in this case is without TSVs. It’s not needed. We just use a cost-effective method. It’s 3D, but it’s done it in a way where are you stacking chips and doing a sidewall or maybe a through-polymer vertical metallization. So you don’t need TSVs because you don’t have the integration density. The driving factor is the form factor.

SMD: How do you make a DNA sensor?
Ramm: A DNA sensor is based on a TMR principal. The integration with a corresponding ASIC is done via 3D integration. In this case, it’s done with a couple of through-silicon vias. If it is cost-effective, it could be a success.

SMD: Where is the industry at with 3D?
Ramm: Concerning the variety of concepts and bonding techniques, we are in very good shape. We have a variety of choices. But you have to make the right choice. You have to choose a reliable 3D integration technology to fulfill the performance and pitch requirements. You need robust processes working in fabrication, not on a power point presentation. There are reliability requirements. They are completely different from product to product. For automotive, you have very high requirements on reliability.

SMD: Where is 3D heading?
Ramm: The answer is that it’s not heading in one direction. You will have a variety of technologies. You will also have a variety of applications. The thing that has to happen soon is that 3D devices must go into fabrication and not face too many problems. This has to be demonstrated. It must go into a product.

SMD: There are still so many challenges, right?
Ramm: The challenge is handling the thin silicon and producing TSVs without any cracks. In the supply chain, not everything can be done by one manufacturer anymore. The reliability must be demonstrated. From my point of view, this is the key problem and challenge—3D must demonstrate the ability to be reliable. It’s one thing to show nice pictures of TSVs, but we have to show it works.

By Ed Sperling
Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of marketing for advanced packaging and nanotechnology at Ultratech. What follows are excerpts of that conversation.

SMD: In manufacturing, one of the roadblocks appears to be bonding/debonding. How much progress is being made?
Matthias: In the past there were many different technologies for the bonding and debonding—thermal, laser, chemically assisted. It’s necessary for a manufacturer to pick one solution, but no one thing has met all the requirements. If there’s one particular process flow, today you can easily do that. You can pick the processors and line them up and manufacture them. But if you want compatibility with every conceivable process flow and every conceivable bond configuration, then it becomes trickier. What is changing is a standardization of the processes of the equipment and material independence standardization. That allows foundries and OSATs to use different materials for different applications. There may be one process for memory where you want to limit the temperature exposure. There may be another for logic and another for IGBTs (insulated gate bipolar transistors), where you want to go to a very high temperature. We have standardized processes and equipment and now it’s an open platform that allows the materials community to develop standardized solutions. There is a lot of movement in this area at the moment and there will be a lot more over the next couple of years.
Patel: This is key because the same OSATs would be doing 2.5D and 3D, where the thickness will be different and sizes will be different on the individual chips. The main issue there is that by bonding and debonding we are not inserting any defects. That will be the main challenge.
Matthias: In the past it was very difficult to think about the process flow because you were locked into one specific process. As this heads toward standardization, you can pick the process that works best. Also, sometimes it doesn’t make sense to ship very fragile wafers across the world.
Patel: I agree. If we can have a bonding/debonding and subsequent manufacturing capability in the same facility, it makes a lot more sense.

SMD: From a systemic standpoint, stacking may be less expensive, even though individual pieces may be more expensive. Does the supply chain have to be reconfigured for this?
Patel: I don’t think it’s a massive change, but it does require a mindset shift. When you look at the cost you can’t look at the individual component costs. You have to look at a product cost. From system-level to product level you have to think differently. It’s very well known that Xilinx’ decision to split a die into four pieces increases the yield. We did some rough numbers and it’s cheaper. If someone asks the cost of an interposer wafer, it’s expensive. But when you consider the cost of the whole package, it’s much more viable.
Smith: Unfortunately, Xilinx is the only case we have in production. Altera’s is a test chip. The system-level discussion for the system companies is very logical. They understand how to put these things together, and what looks to us like a major change is for them an incremental step.
Ranjan: There are also power savings in this. There are things that go onto a single-chip solution that will require higher power and greater thermal management requirements. That’s all resolved in 2.5D and 3D.
Smith: There are companies that are mixing together higher power and lower power chips to come up with what is an overall lower-power device.
Ranjan: TSVs also can handle some of the heat distribution, too.
Smith: IBM was talking about heating an entire building out of the microfluidic heat exchangers. It’s interesting research.

SMD: Presumably we will have different materials involved in stacked die. Will that go together as smoothly as CMOS on CMOS?
Patel: Image sensors are an example where they do go together well, but you do have to make sure the stresses of the integration don’t affect performance. Compatibility will be a key factor in integration.
Smith: TSVs and thermal expansion have to be analyzed by the manufacturers. There is already a lot of research out there. There are whole conferences on this. It does affect what else you include in the stack and what you bond it with.

SMD: How far are we away from standards in this area?
Patel: There are standards being created. Sematech is publishing a dashboard of different standards. From my perspective we need to bring standards together across the supply chain and make it more workable. That needs to happen first. Once you have baseline standards, you can bring in more technical standards.
Smith: From an EDA point of view, standards are still premature. The IEEE test standard is going slowly, and that’s partly because there is no driver at this point. We’ll see the major companies building these stacks gain experience, and in the process of learning we’ll start to share that. Then it can become standardized.
Pateras: You attempt to use one source for your design automation, at least initially.
Smith: Even today companies mix and match tools using standard interfaces.
Pateras: Or you do them ad hoc and then merge these standards.

SMD: Are any standards emerging on the manufacturing side?
Ranjan: For us, we are moving into the TSV space quickly. We already have equipment out there for production and R&D. There is nothing that makes it prohibitive to use this equipment right now. Standards are more meaningful on the design side. On the manufacturing side, there are no barriers today.
Matthias: In terms of standardization, the big breakthrough in the last 12 months was in bonding/debonding with the material-independent concept. In terms of the actual specification of the die and bonding together, there are already de facto standards as to what kinds of bonds you can use. At the wafer level, which is a couple years out, you’re using an oxide interface. The bonding becomes a standardized step.

SMD: When will 2.5D and 3D start showing up?
Ranjan: 2.5D is still a few years away. There is some production right now, but for meaningful volume—maybe 20,000 to 50,000 wafers per month—it’s at least two years out. TSVs are a couple years beyond that. That’s what we’re using as a projection for our equipment based on what we’ve heard from our customers.
Smith: In EDA we measure tapeouts. Aside from a few IDMs, we’re still in the test-chip phase this year. But we’re expecting early production by the end of next year, if not earlier. We’ve seen some early examples from Xilinx and Altera. The graphics guys will come next. So 2.5D already is well on the way to becoming useful. For 3D, aside from a couple examples, we won’t see that until 2015.
Matthias: By the end of next year we believe all the major players will have production capacity for both 2.5D and 3D. That’s probably not 20,000 to 50,000 wafers per month, but there will be production capacity at every player that wants to take a leading role. By the end of next year there will be a supply chain for 2.5D and 3D, although probably at a lower volume and for high-end products.
Patel: For 2.5D, 2014 will be a very interesting year. By the end of 2013 the capability will be in place. Designs already are being considered and tried out. 3D mainly depends on memory standards and memory adoption. We’ll see a package-on-package and memory-on-logic configuration first. 3D memory has its own route, which is ahead of that. 3D memory on logic could be late 2014.
Pateras: From a tapeout point of view, 2.5D is happening this year. We have customers taping out 2.5D. For 3D, we’re seeing design activity for memory on logic. Next year we’ll see some tapeouts. There is no real activity in logic on logic yet.

Making 3D TSVs more accessible, STATS ChipPAC Ltd. reported Tuesday that it has qualified it’s through silicon via (TSV) capabilities for 300mm mid-end manufacturing operation and transition to low volume manufacturing.  The company said it is working with multiple customers on TSV development programs with current 3D TSV development and customer qualification activities that include devices at the 28nm silicon node, application processors and graphic processors utilizing TSV for the high performance Wide I/O memory interface required by higher bandwidth applications for the mobile market.

Dr. Han Byung Joon, executive vice president and chief technology officer at STATS ChipPAC said in a statement, “The need for higher levels of integration, improved electrical performance, reduced power consumption, faster speed, smaller device sizes and shorter interconnects is forcing a shift to more complex 2.5D and 3D package designs utilizing TSV technology. TSV technology will be a key requirement in the convergence of mobile communication and computing functionality in devices such as smartphones and tablets. This is a trend which is expected to drive rapid growth and adoption of TSV technology.”

The company noted that the mid-end TSV process flow occurs between the wafer fabrication and back-end assembly process supporting the advanced manufacturing requirements of 2.5D and 3D packaging including wafer level, flip chip and embedded technologies and now has mid-end manufacturing capacity in place in Singapore and is working with customers on the production qualification of 2.5D and 3D packaging designs.