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Posts Tagged ‘193 immersion’

What’s the Next-Gen Litho Tech? Maybe All of Them

Thursday, February 25th, 2016

By Jeff Dorsch, Contributing Editor

The annual SPIE Advanced Lithography symposium in San Jose, Calif., hasn’t offered a clear winner in the next-generation lithography race. It’s becoming clearer, however, that 193i immersion and extreme-ultraviolet lithography will co-exist in the future, while directed self-assembly, nanoimprint lithography, and maybe even electron-beam direct-write technology will fit into the picture, too.

At the same time, plasma deposition and etching processes are assuming a greater interdependence with 193i, especially when it comes to multiple patterning, such as self-aligned double patterning, self-aligned quadruple patterning, and self-aligned octuple patterning (yes, there is such a thing!).

“We’ve got to go down to the sub-nanometer level,” Richard Gottscho, Lam Research’s executive vice president of global products, said Monday morning in his plenary presentation at the conference. “We must reduce the variability in multiple patterning,” he added.

Gottscho touted the benefits of atomic level processing in continuing to shrink IC dimensions. Atomic level deposition has been in volume production for a decade or more, he noted, and atomic level etching is emerging as an increasingly useful technology.

When it comes to EUV, “it’s a matter of when, not if,” the Lam executive commented. “EUV will be complementary with 193i.”

Anthony Yen, director of nanopatterning technology in the Infrastructure Division of Taiwan Semiconductor Manufacturing, followed Gottscho in the plenary session. “The fat lady hasn’t sung yet, but she’s on the stage,” he said of EUV.

Harry Levinson, senior director of GlobalFoundries, gave the opening plenary presentation, with the topic of “Evolution in the Concentration of Activities in Lithography.” He was asked after his presentation, “When is the end?” Levinson replied, “We’re definitely not going to get sub-atomic.”

With that limit in mind, dozens of papers were presented this week on what may happen before the semiconductor industry hits the sub-atomic wall.

There were seven conferences within the symposium, on specific subjects, along with a day of classes, an interactive poster session, and a two-day exhibition.

The Alternative Lithographic Technologies conference was heavy on directed self-assembly and nanoimprint lithography papers, while also offering glimpses at patterning with tilted ion implantation and multiphoton laser ablation lithography.

“Patterning is the battleground,” said David Fried, Coventor’s chief technology officer, semiconductor, in an interview at the SPIE conference. He described directed self-assembly as “an enabler for optical lithography.”

Mattan Kamon of Coventor presented a paper on Wednesday afternoon on “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node.”

DSA could be used in conjunction with SAQP or LELELELE, according to Fried. While some lithography experts remain leery or skeptical about using DSA in high-volume manufacturing, the Coventor CTO is a proponent of the technology’s potential.

“Unit process models in DSA are not far-fetched,” he said. “I think they’re pretty close.  The challenges of EUV are well understood. DSA challenges are a little less clear. There’s no ‘one solution fits all’ with DSA.” Fried added, “There are places where DSA can still win.”

Franklin Kalk, executive vice president of technology for Toppan Photomasks, is open to the idea of DSA and imprint lithography joining EUV and immersion in the lithography mix. “It will be some combination,” he said in an interview, while adding, “It’s a dog’s breakfast of technologies. Don’t ever count anything out.”

Richard Wise, Lam’s technical managing director in the company’s Patterning, Global Products Groups CTO Office, said EUV, when ready, will likely be complementary with multipatterning for 7 nanometer.

Self-aligning quadruple patterning, for example, was once considered “insanity” in the industry, yet it is a proven production technology now, he said.

While EUV technology is “very focused on one company,” ASML Holding, there is a consensus at SPIE that EUV’s moment is at hand, Wise said. Intel’s endorsement of the technology and dedication to advancing it speaks volumes of EUV’s potential, he asserted.

“Lam’s always excelled in lot-to-lot control,” an area of significant concern, Wise said, especially with all of this week’s talk about process variability.

What will be the final verdict on the future of lithography technology? Stay tuned.

Optimism Reigns at SPIE Lithography Conference, Despite Challenges

Tuesday, February 23rd, 2016

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By Jeff Dorsch, Contributing Editor

Semiconductor manufacturing and design is growing increasingly complicated and just plain hard. Everyone knows that. The bad news is it’s only going to get worse.

Relax, there are many smart people gathered in San Jose, Calif., this week for the SPIE Advanced Lithography Symposium to discuss the challenges and figure out how to surmount them.

The changes required in lithography and related technologies to continue IC scaling promise to be painful and costly. Mitigating the pain and the cost is a common theme at the SPIE conference.

The annual SPIE Advanced Lithography conference is often dominated by discussions on the state of extreme-ultraviolet lithography (EUVL). In presentations on Sunday and Monday, the theme was generally the same as 2015 – EUV is making progress, yet it’s still not ready for high-volume semiconductor manufacturing.

Intel Fellow Mark Phillips said the technology has seen “two years of solid progress,” speaking Sunday at Nikon’s LithoVision 2016 event. He added, “There’s no change in Intel’s position: We’ll use EUV only when it’s ready.”

Anthony Yen of Taiwan Semiconductor Manufacturing covered the 30-year history of EUV development in his Monday morning presentation at the SPIE conference. Asked during the question-and-answer session following the presentation on when the world’s largest silicon foundry will use EUV, Yen stuck to the official company line of implementing EUV in production for the 7-nanometer process node, after some involvement at 10nm.

Seong-Sam Kim of Samsung Electronics also sees EUV realizing its long-aborning potential at 7nm, a node at which “argon fluoride multipatterning will hit the wall.” He touted the 80-watt power source Samsung has achieved with its NXE-3300 scanner from ASML Holding, saying it had maintained that level over more than eight months.

Intel’s Britt Turkot reported 200W source power “has been achieved recently,” and said the tin droplet generator in its ASML scanner has been significantly improved, increasing its typical lifetime by three times. EUV has demonstrated “solid progress,” she said, including ASML’s development of a membrane pellicle for EUV reticles.

While work with the ASML scanner on Intel’s 14nm pilot fab line has been “encouraging,” Turkot said, she added, “We do need to keep the momentum going.” Intel sees EUV entering into volume production with 7nm chips, according to Turkot. “It will be used when it’s ready,” she said.

EUV technology has shown “good progress” in productivity, while its availability and cost considerations have “a long way to go,” Turkot concluded, adding, “We need an actinic solution for the long term.”

An industry consensus has emerged that EUV will be used with ArF 193i immersion lithography in the near future, and this trend is likely to continue for some time, according to executives at the SPIE conference. There may also be wider adoption of directed self-assembly (DSA) and nanoimprint lithography technology, among other alternative lithography technologies.

Mark Phillips of Intel pointed to complementary implementation of EUV and 193i. “We must use EUV carefully,” he said. “We need to replace three-plus 193i masks.” Phillips added, “EUV can’t be applied everywhere affordably. 193i will continue to be used whenever possible.”

Nikon executives touted the capabilities of their new NSR-S631E ArF immersion scanner, introduced just before the SPIE conference. The new scanner can turn out 250 wafers per hour, and can be pushed to 270 wph with certain options, according to Nikon’s Ryoichi Kawaguchi.

Yuichi Shibazaki of Nikon said the company will next year introduce the S63xE scanner, improving on S631E.

For all the challenges of transitioning to 7nm and beyond, executives at SPIE remain optimistic about solving the issues of 193i multipatterning, DSA, and EUV. Harry Levinson of GlobalFoundries said in response to a question, “The ultimate resource is the human mind.”

Lithography: What are the alternatives to EUV?

Thursday, August 28th, 2014

By Pete Singer, Editor-in-Chief

EUV received a recent boost with IBM reporting good results on a 40W light source upgrade to its ASML NXE3300B scanner, at the EUV Center of Excellence in Albany. The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.  In the first 24 hours of operation after the upgrade, 637 wafer exposures were completed in normal production lot mode. Dan Corliss, the EUV Development Program Manager for IBM, called it a “watershed moment.”

Critics, most notably analyst Robert Maire of Semiconductor Advisors, said it was “not that much of a real increase in power and certainly no breakthrough, just incremental improvement.” He adds: “We still don’t have the reticle “ecosystem,” the resist and many other components to make for viable, commercial EUV production. We are still a very long way away and this does not change the view that EUV will not be implemented at 10nm.” The 10nm node is slated to go into production in late 2015/early 2016.

Yet EUV proponents remain optimistic. Kevin Cummings, the director of lithography at SEMATECH, said “It is good news indeed to hear that IBM in conjunction with ASML has met/exceeded their projected productivity. It is clear to this industry that the EUV LPP source was not meeting the desired schedule and the source improvements timelines were over promised. However this announcement give us some confidence that we are making progress against that schedule. In addition, this milestone is significant in that it allows the wafer throughput needed to continue EUVL HVM development. With the throughputs obtained on the scanner and the recent successes from SEMATECH on zero defect mask blanks and low-dose high-resolution resists now is an excellent time to take advantage of the Albany NY based capability to develop the materials and processes that will be needed for EUVL manufacturing.”

Luc Van den hove, president and CEO of imec, described EUV as a cost-effective lithography approach that is “absolutely needed.” In terms of imaging performance, imec has been characterizing some of the latest hardware together with ASML and have showed very good resolution performance of 13nm half pitch and 22nm contact holes. “With double patterning, we have even demonstrated 9nm half pitch,” Van den hove said. “Who would have thought a couple of years ago that this would be realizable with lithography?”

An Steegen, senior vice president of process technology at imec, said the ideal entry point for EUV is the 10nm node (or N10 using imec’s terminology). “If you look at the cost calculation, the best entry point for EUV is actually at N10 because you can replace triple patterning layers in immersion with a single patterning layer in EUV,” Steegen said. Since that will come relatively soon with early production occurring toward the end of 2015 and in early 2016, that means that likely the whole development phase will have already been built on immersion and multi-patterning. “Likely you will see on the most difficult levels, a swap, an introduction of EUV at the most critical levels later on in manufacturing for N10,” Steegen said.

Interestingly, industry-leader Intel has said that it will not use EUV for 14nm, and even sees a path to 10nm without EUV. At the Intel Developer’s Forum in 2012, Mark Bohr, director of Intel’s technology and manufacturing group said 10nm “would require quadruple patterning for some mask layers but it’s still economical.”

FIGURE 1. Multi-patterning can achieve sub-10nm dimensions. Source: Applied Materials.

FIGURE 2. Multi-patterning adds many process steps, and cost. Source: ASML.

FIGURE 1 shows that the use of spacers can enable sub-10nm dimensions without EUV. FIGURE 2 shows multi-patterning adds to process cost and complexity.

Earlier this year, at the SEMI Northeast Forum held in North Reading, MA, Patrick Martin, Senior Technology Director at Applied Materials, talked about scaling and the rising cost and complexity of patterning. “There’s a lot of talk in the industry about how scaling is dead,” he said. I think a lot of the discussions are if we look at the current architectures entitlements – finFET related technologies that scale to 7nm and 5nm, and the complexity associated with litho, driving those types of cost models, I would have to agree. But the argument is really going to be on architecture entitlement. How the devices are going to adapt to these pattern complexity limited challenges.”

Terry Lee, the chief marketing officer for the DSM business unit at Applied Materials says continued scaling will not be driven as much by lithography, but by 3D. “Scaling used to be enabled by lithography,” he said in a presentation at this year’s Semicon West. “What we’re seeing is the move to enable scaling using both materials and 3D device architectures.” 3D devices include FinFETs, 3D NAND DRAMs with buried word lines and bit lines. These devices represent “the drive to further scale on a third dimension versus scaling using lithography on a horizontal plane,” Lee said. Appled Materials recently introduced a several new products aimed at the 3D device market, including the Producer XP Precision CVD system.

“We’re really in a dilemma when it comes to semi-related production capability,” Martin said. The device features are much smaller than the wavelength that we’re using. We’re into these complex processing related technologies that require double patterning, triple patterning, multiple patterning. The great equalizer here is EUV. If we can ever get to EUV-related manufacturing capability, it gets us to a regime where the devices are relatively the same size as the wavelength of light. The problem is that it’s been delayed. The challenge is if it doesn’t hit 10nm, we’re looking at 7nm. If we start looking at the insertion opportunity for EUV at 7nm and 5nm, we’re now below wavelength. 13.5 nm is the wavelength of EUV. The complexities associated with double patterning come back into play,” Martin added.

The EUV mask challenge

The next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. According to Veeco’s Tim Pratt, Senior Director, Marketing, the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV. “Based on the yield today, the mask blank manufacturing capacity can’t produce enough mask blanks to support the ASML scanners that they’re planning to ship,” Pratt said. “ASML is going to be delivering some light source upgrades in the field and when those start happening, the effective total wafer throughput of EUV scanners in the field is going to multiply and there’s just not the supply of usable mask blanks to be able to support those.”

The requirement for 2015 is to have zero blank defects larger than 62nm. SEMATECH in 2012 reported work showing eight defects larger than 50nm. “A lot of progress being made but the elusive zero defects has not yet been hit,” Pratt said. Veeco, which is the sole supplier of EUV multilayer deposition tools, has plans to upgrade the existing Odyssey tool and launch a new platform in the 2017/2018 timeframe.

FIGURE 3. EUV masks are considerably more complicated than conventional photomasks. Source: Veeco.

FIGURE 3 shows an EUV mask, which is considerably more complicated than conventional photomasks.

What could derail the EUV ramp, according to Pratt, is a supply of defect-free mask blanks. “EUV is, despite many years and many dollars of investment, not yet in production. The two main gaps are the EUV light sources and the defects on the mask. As they start to make progress, people start to look more seriously at the list of things to worry about for EUV going to production.

The e-beam alternative

There are only a few alternatives to EUV and complex (and costly) mutli-patterning approaches: multi-e-beam (MEB), nanoimprint and directed self-assembly. Electron beam lithography with a single beam has been used for many years for mask writing and device prototyping, and tools available from a number of companies, such as Advantest, IMS, JEOL and Vistec.

Single-beam writing has never been able to compete with massively parallel optical systems in throughput and cost. Now, TSMC’s Burn Lin says that the time for e-beam lithography has arrived. Why? Digital electronics can affordably provide a gigabit per second data rate in a manageable space, enabling very high wafer throughput. Microelectrical mechanical systems and packaging techniques have advanced sufficiently to support a several order of magnitude increase in beam number and high-speed beam writing. And e-beam techniques generally offer higher resolution than optical systems. [1] Last year, TSMC and KLA-Tencor presented a reflective e-beam lithography (REBL) system that can potentially enable multiple-e-beam direct-write for high-volume manufacturing.

Multiple beam systems are also being developed by Multibeam Corp. (the well known David Lam is CEO), IMS and MAPPER. MAPPER was founded in 2000 by Professor Pieter Kruit and two of his recent graduates Marco Wieland and Bert Jan Kampherbeek.

What’s intriguing about e-beam direct write is that it could be used in conjunction with more conventional immersion lithography. Yan Borodovsky, Intel Corporation Sr. Fellow and Director of Advanced Lithography, calls it “complementary lithography.” He says that EBDW could be used instead of EUV to break the continuity of the grating made using 193i with pitch division. In addition to again maintaining the benefits of mature 193i on the critical layer, this solution has lower mask costs (no mask required for grating cutting and vias), and the escalating cost of the mask-making infrastructure is avoided.

He reported that EBDW could also be used instead of EUV for the complementary solution to break the continuity of the grating made using 193i with pitch division. In addition to again maintaining the benefits of mature 193i on the critical layer, this solution has lower mask costs (no mask required for grating cutting and vias), and the escalating cost of the mask-making infrastructure is avoided.

An organization that is focused on developing e-beam technology for mask writing and direct write is the E-beam Initiative (www.ebeam.org).

Nanoimprint

Step and Flash Imprint Lithography (SFIL), a form of ultraviolet nanoimprint lithography (UV-NIL), is recognized for its resolution and patterning abilities. It is one of the few next generation lithography techniques capable of meeting the resolution requirements of future semiconductor devices. Austin-based Molecular Imprints, now a wholly owned subsidiary of Canon, has successfully commercialized the technology. Molecular Imprints invested $165 million over the last decade on platforms, materials, templates and applications.

In 2004, Canon began conducting research into nanoimprint technology to realize sub-20nm high-resolution processes began carrying out joint development with Molecular Imprints and a major semiconductor manufacturer in 2009. Canon says NIL offers such benefits as high-resolution performance, exceptional alignment accuracy and low cost. However, others report that many integration issues such as defectivity, throughput, and overlay must be resolved before SFIL can be used for leading-edge semiconductor high volume manufacturing.

DSA is very promising

Imec’s Van den hove described direct self-assembly (DSA) as “very promising” and Steegen said work there has largely focused on reducing defectivity. In DSA, resists that contain block copolymers are deposited on top of guiding structures. The self-directed nature of the process results in very regular patterns with very high resolution.

The trick with DSA is that it requires a double exposure to take away the random patterns at the edge of the device, and the resolution needed for this “cut mask” is also very high. “We’re convinced that it’s not a replacement for EUV or any high resolution lithography technique. We are very convinced it will be used in conjunction with EUV,” Van den hove said. “It certainly keeps the pressure on EUV very high.”

Steegen described DSA as a complimentary litho technique that is having quite some momentum. The process starts with a “relaxed” guiding pattern on your wafer.  Then, depending on the polymer length in the block copolymer, the space in between the guiding structure is replicated into multiple lines and spaces. “The defectivity of these materials are going to be key to bring the defects down. Our year end target is 60 defects/cm2 and this needs to go down even further next year,” she said.

Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” Steegen said. Imec is already looking at where DSA levels could be inserted into the logic N7 flow, with fins and spacers being primary targets. Steegen said the Metal1 level would be a challenge due to its irregular pattern. “That makes it not easy to be replaced with DSA, but we’re looking into techniques to do that,” she said.

Here’s how imec summed up DSA readiness:

• Good progress in material selection and integration flow optimization for line-multiplication down to 14nm, pattern transfer into bulk Si demonstrated.

• First templated DSA process available using SOG/SOC hard mask stack.

• Focus on defectivity reduction & understanding, currently at 350 defects/cm2, YE13 target 60 def/cm2

• Alignment and overlay strategy needs to be worked out

• First N7 implementation levels identified: Finfet (replace SADP EUV or SAQP 193i) and Via (replace EUV SP/DP or 193i LE3).

Conclusion

Hopes remain high for EUV, but long delays has caused attention to shift to possible alternatives. Multi-level patterning is costly but it works; Intel, for example, says it will soon have 14nm devices in production without using EUV. Mutli-ebeam work continue apace, and we could see a role in direct write e-beam in a complementary approach with conventional lithography. Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. Some new device structures, such as vertical NAND and FinFETs, take the pressure off of lithography, but create challenges in other process areas, such as deposition and etch.

Blog Review October 21 2013

Monday, October 21st, 2013

The readiness of EUV lithography is later than hoped, but appears to be on time for insertion into the 10nm node, which is slated to go into production in late 2015/early 2016. “I’m very convinced that very soon EUV will be ready to enter manufacturing,” said Luc Van den hove, president and CEO of imec, as reported by Pete Singer.

In an earlier blog, Veeco’s Tim Pratt, Senior Director, Marketing, said that indeed the next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. He said that the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV.

Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” said An Steegen, senior vice president of process technology at imec.

EUV readiness also been the focus of several blogs by Vivek Bakshi. Earlier this year, he predicted that 50 W sources will be ready and working in NXE3300B sometime in 2014, corresponding to 43 WPH throughput. 100 W sources will be ready in 2015 or 2016 corresponding to 73 WPH. “The readiness of 250 W EUV sources cannot be safely predicted, unless we see 100 W sources ready and have identified the issues to ensure that they are no showstoppers. I am not convinced that present approaches can get to 500 W sources. It is easy to put them on roadmaps, but delivering them is another question,” he said.

Intel is far ahead of anyone else when it comes to putting 14nm devices into production. However, even Intel finds it challenging. Speaking on a quarterly call with analysts, newly elected CEO Brian Krzanich said 14nm rollout was “about a quarter behind our projections.” He said defects were the problem. “As a result, we are now planning to begin production in the first quarter of next year,” as Pete Singer reported.

Intel already has 3D finFETs in production, and  FinFETs will likely become the logic technology of choice for the upcoming generations, with high mobility channels coming into play for the 7 and 5nm generation (2017 and 2019).

Brian Krzanich also said that Intel remained committed to the transition to 450mm wafers, saying: “We have not changed our timing. We are still targeting the second, latter half of this decade.” At Semicon Europa week, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.

Phil Garrou reports on developments from Semicon Taiwan 2013 of interest to the IC packaging community. The Market Trends Forum chaired by Dr. Burn Lin of TSMC, included a report on DRAM Status (continued consolidation) by Charlie Chan of Morgan Stanley; Nicolas Gaudois Managing Director of UBS Investment Research looked at the “The End of the High End Smartphones Run,” and Dan Tracy of SEMI provided the Packaging Materials Outlook.