Part of the  

Solid State Technology

  and   

The Confab

  Network

About  |  Contact

Headlines

Headlines

Logic Densities Advance at IEDM 2017

By Dave Lammers

The 63rd International Electron Devices Meeting brought an optimistic slant to transistor density scaling. While some critics have declared the death of Moore’s Law, there was little evidence of that — on the density front at least — at the IEDM, held Dec. 2-6 in San Francisco.

And an Intel engineering manager gave a presentation at IEDM that took a somewhat optimistic view of EUV lithography readiness, auguring further patterning improvements, starting with contacts and vias.

GlobalFoundries, which is skipping the 10nm node, presented its 7nm logic technology, expects to move into manufacturing in mid-2018. John Pellerin, vice president of global R&D, said the foundry has worked closely with its two lead customers, AMD and IBM, to define a high-performance-computing 7nm logic technology that achieves a 2.8X improvement of routed logic density compared with its 14nm technology.

Pellerin said the current 7nm process of record (POR) delivers “the right mix of performance, power, and area (PPA),” adding that GlobalFoundries plans to bring in EUV patterning at an undefined later point in the 7+ generation for further improvements.

Contact Over Active Gate

Chris Auth, director of advanced transistor development at Intel Corp., described a 10nm logic technology that sharply increased the transistor density compared with the 14nm generation, partly due to a contact-over-active-gate (COAG) architecture. The 10nm ring oscillator performance was improved by 20 percent compared with the comparable 14nm test vehicle.

Chris Auth, who presented Intel’s 10nm technology paper at IEDM, was surrounded by questioners following the presentation.

Auth said the COAG approach was a key contributor to Intel’s ability to increase its transistor density by 2.7 times over the company’s previous generation, to 100 million transistors per square millimeter of silicon. While the traditional approach puts the contact via over the isolation area, COAG places the contact via directly over the gate. Auth said the approach does require a second etch stop layer and other process complexities, but contributes “a sizable 10 percent reduction in area.” Elimination of the dummy gate for cell boundary isolation, and the use of cobalt at three layers (see related story), also contributed.

While there has been much hand wringing in the industry over the costs involved with multi-level patterning, Auth didn’t appear phased by it. Intel used a self-aligned quad patterning (SAQP) scheme to create fins with a tight pitch. The SAQP approach required two sacrificial layers, with lithography defining the first large pattern and four additional steps to remove the spacers and create the final lines and spaces.

The Intel 10nm fins are 46nm in height.

The SAQP approach starts by exposing a 130nm line, depositing the two spacers, halving the pattern to 68nm, and again to 34nm. “It is a grating and cut process similar to what we showed at 22nm, except it is SAQP instead of SADP,” using patterning to form a grating of fins, and cutting the ends of the fins with a cut mask.

“There were no additional lithography steps required. The result was fins that are tighter, straighter, and taller, with better drive current and matching” than Intel’s 14nm-generation fins, he said. Intel continued to use self-aligned double patterning (SADP) for M 2-5, and for gate patterning.

GlobalFoundries — which has been in production for 18 months with the 14nm process used by AMD, IBM, and others — plans to ramp its 7nm logic generation starting in mid-2018. The 7nm high-density SRAM cell measures .0269 um2, slightly smaller than TSMC’s published 7nm cell, while Intel reported a .0312 um2 cell size for its 10nm process.

Intel argues that the traditional way of calculating density improvements needs to be replaced with a metric that combines NAND and scan flip-flop densities. (Source: Intel)

GlobalFoundries chief technology officer Gary Patton said, “all of us are in the same zip code” when it comes to SRAM density. What is increasingly important is how the standard cells are designed to minimize the track height and thereby deliver the best logic cell technology to designers, Patton said.

EUV Availability Needs Improvements

Britt Turkot, senior principal engineer at Intel, discussed the readiness of EUV lithography at an IEDM session, giving a cautiously bullish report. With any multi-patterning solution for leading-edge silicon, including etch and CMP steps, placement error is the biggest challenge. With quad patterning, Turkot said multiple masks are involved, creating “compounded alignment errors.”

EUV has its own challenges, including significant secondary ions from the EUV photons. The key challenge for much of the decade, source power, seems to be partially resolved. “We are confident that the 250 Watts of source power needed for volume manufacturing will be ready once the field tools are upgraded,” she said.

Pellicles may be another challenge, with ASML expected to have a polysilicon-based pellicle ready in time for EUV production. However, she said a polysilicon membrane “does give quite a hit to the transmissivity” of the mask. “The transmissivity impact is quite significant,” she acknowledged during the Q&A period following her talk.

Intel has succeeded in repairing some mask defects, Turkot said, and implements pattern shifting so that other defects do not impinge on the patterned wafer.

Asked by a member of the audience about EUV availability or up-time, Turkot said “one day, availability can be great,” and less than good on other days, with “long unscheduled downs.” Intel is predicting 88 percent availability next year, she said in response to a question.

Pellicle Needed for Wiring Layers

Scotten Jones, president of semiconductor cost consultancy IC Knowledge (Boston), said companies may be able to get by without a pellicle for EUV patterning of contacts and via layers late next year. However, a pellicle will be needed for patterning the lower-level wiring layers, absorbing 10-15 percent of the photons and impacting EUV patterning throughput accordingly.

“Companies can do the contacts and vias without a pellicle, but doing the metal layers will required a pellicle and that means that a ton of work still needs to be done. And then at 5nm, the dose you need for the resist goes up dramatically,” Jones said, adding that while it will take some time for ASML to roll out the 250 W source, “they should be able to do it.”

GlobalFoundries will take possession of its second EUV scanner in December 2017, while Intel is believed to own four EUV systems.

Pellerin said GlobalFoundries defined the ground rules for its 7nm process so that the foundry can do a phased implementation of EUV without causing its customers “design discontinuity, bringing a benefit to design costs.”

John Pellerin, v.p. of R&D, said GlobalFoundries plans a phased implementation of EUV without “design discontinuity.”

The foundry will first do the hole levels and then move into the tight-pitch metal levels as mask defectivity improves. “The mask ecosystem needs to evolve,” Pellerin said.

Cost-per-Function on Track

In a keynote speech at IEDM, Lisa Su, the CEO of Advanced Micro Devices, said over the last 10 years the semiconductor industry has succeeded in doubling transistor density every 2-2.4 years. But she said the performance gains have been much smaller. “We are making progress, but it is taking a tremendous amount of work,” said Su, who received a best paper award at the IEDM 25 years earlier.

About 40 percent of the CPU performance improvement now comes from pure process technology, Su said, while the remainder comes from better microarchitectures, power management, and integration of system components such as an on-chip memory controller. While instructions per cycle are increasing at a 7 percent annual clip, Su said “the tricks have run out.”

Overall, the leading semiconductor companies seem to continue to make progress on transistor density. And costs per transistor may also be on track. Kaizad Mistry, co-director of logic technology development at Intel, contends that with its Intel’s 10nm process Intel’s per-transistor costs are actually better than the historical  curve.

Jones said the IC Knowledge cost analysis of TSMC’s processes indicates TSMC also is hewing to historical improvements on the per-transistor cost front. However, the foundries are catching up to Intel.

Intel Cadence Lagging

“What really strikes me is that Intel brought out its 45nm process in 2007, 32nm in 2009, and 22nm in 2011, but then it took three years to do 14nm. We are about to be in the year 2018, and Intel still doesn’t have its 10nm process done. It is a very nice process, but it is not out yet, and TSMC’s 7nm process is ramping right now. By the time Intel gets to 7nm, the foundries may be at 3nm. GlobalFoundries skipped a generation but is ramping its 7nm next year. All will have processes competitive to Intel at the same time, or even earlier,” Jones said.

While foundries such as GlobalFoundries, Samsung, and TSMC may be able to quickly offer advanced logic platforms, the wider semiconductor industry faces design cost challenges, Jones said. “Yes, the cost-per-transistor is going down, and that’s nice, but the cost of a design with finFETs is in the 100-million-dollar range. Intel can do it, but many smaller companies can’t afford to design with FinFETs.”

That is why both GlobalFoundries and Samsung are offering FD-SOI based platforms that use planar transistors, reducing design costs.

“The Internet of Things market is going to be nine million things, at relatively low volumes. IoT companies are finding it hard to justify the cost of a FinFET design, but with the cheaper design costs, SOI gives them an economical path,” Jones said.



Tags: , , , , , , , , , ,

Leave a Reply