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Mentor Graphics Offers Tanner Calibre One Verification Suite for the Tanner Analog/Mixed-Signal IC Design Environment

Mentor Graphics® Corporation announced the Tanner Calibre One IC verification suite as an integral part of the Tanner™ analog/mixed-signal (AMS) physical design environment, creating an easy path to the proven capabilities of Calibre® verification tools for Tanner EDA’s user base. This results in a dramatically-improved IC design and verification solution for Tanner customers by providing tightly-integrated access to Calibre’s physical and circuit verification, exclusively within the Tanner L-Edit™ layout environment.

The Calibre platform is the industry-leader for physical verification and is qualified for sign-off by every major IC foundry and the Tanner Calibre One verification suite uses the same Calibre design kits. Customers that already have stand-alone Calibre licenses, and would like to consider the Tanner design environment, can continue to use the pre-existing Calibre-Tanner interfaces. However, offering an additional, custom integration between Calibre and the Tanner AMS IC design flow provides an invaluable option for Tanner IC designers, giving design teams the access they need to confidently tape out their designs.

“We’ve seen a dramatic increase in the productivity of our layout team thanks to the seamless interaction of L-Edit and the Tanner Calibre One verification suite,” said Stefan Lauxtermann, President of Sensor Creations Inc. “Our customers greatly value that we employ Calibre and that there is a one-to-one correspondence between the final DRC by the foundry and the Tanner design process that we use.”

The Tanner Calibre One verification suite includes the following products:

  • Calibre nmDRC™ (hierarchical design rule checking) ensures the physical layout can be manufactured. This industry-leading tool provides fast cycle times and innovative design rule capabilities.
  • Calibre nmLVS™ (hierarchical layout versus schematic) checks that the physical layout is electrically and topographically the same as the schematic. It improves designer productivity by providing actual device geometry measurement and sophisticated interactive debugging capabilities to ensure accurate verification.
  • Calibre xRC™ (parasitic extraction) verifies that layout-dependent effects do not adversely affect the electrical performance of the design, delivering accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.

In addition, the Calibre RVE™ tool brings the solution together, providing a graphical results viewing environment that reduces debug time by visually identifying design issues instantly and cross-selecting the associated issue in Tanner’s layout and schematic capture tool.

The Tanner IC design suite supports analog, mixed-signal, and MEMS design in one complete, highly-integrated, end-to-end flow. Designers capture the schematic, perform analog and mixed-signal simulation, and lay out the physical design within this unified flow. With the addition of the Tanner Calibre One verification suite, each designer using the Tanner IC flow can interactively invoke an individual Calibre tool in order to verify the design.

“Tanner Calibre One gives designers using L-Edit the highest confidence possible that their tape outs will be successful,” says Greg Lebsack, General Manager of Tanner operations at Mentor Graphics. “We are thrilled that key capabilities of the industry-leading Calibre suite are now available to everyone in our global Tanner customer base.”

The Tanner Calibre One design flow will be demonstrated at the 2016 Design Automation Conference (DAC) in the Tanner EDA booth (#1828).



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