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What to See at the SPIE Advanced Lithography Show

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By Gandharv Bhatara, Calibre Semi-Manufacturing Marketing Manager

The SPIE Advanced Lithography conference, from Tuesday, February 23, to Thursday, February 25, offers an incredible amount of technical information in a few long, fun days.  This year, Mentor Graphics has a large presence at SPIE Advanced Lithography to demonstrate our technical dominance in three computational lithography solutions – multipatterning with immersion lithography, EUV, and directed self-assembly. These are the three viable candidates at the advanced technology nodes (< 10nm), and Mentor continues to invest and develop them.

Mentor is engaged in deep partnerships will several leading-edge foundries and presents a multitude of papers that are written jointly with leading-edge foundries:

  • Samsung — “A random approach of test macro generation for early detection of hotspots”
  • GLOBALFOUNDRIES
    • “Directed self-assembly (DSA) compliant correction flow with immersion lithography”
    • “Source mask optimization using 3D mask and compact resist models”
    • “Multi-layer VEB model: capturing interlayer etch process effects for self-aligned via in multipatterning process scheme”
    • “EUV implementation of model-based assist features in contact patterns”
    • SMIC
      • “A novel full chip process window OPC based on matrix retargeting”
      • “Design space exploration for early identification of yield limiting patterns”
      • SK Hynix — “Advanced DFM application for automated bit-line pattern dummy

Mentor also partners with leading academia, universities, research institutes and experts in the area of lithography and has papers co-written with:

  • IBM Thomas J. Watson Research Center — “Ultimate 2D resolution printing with negative-tone development”
  • Chris Mack — “Modeling metrology for calibration of OPC models”
  • Rochester Institute of Technology — “An automated image-based tool for pupil plane characterization of EUVL tools”
  • China’s Institute of Microelectronics — “Design technology co-optimization for 14/10nm metal1 double patterning layer”

What should become clear from the SPIE conference lineup, is that Advanced Lithography now extends well past mask synthesis and RET/OPC and into DFM, design enablement, and design-technology co-optimization (“Patterns-based DTCO flow for early estimation of lithographic difficulty using optical image processing techniques”).

Mentor is well positioned as a technology leader in all these areas. Designs today demand integrated solutions, not just point tools. That’s why we have developed an entire post-tapeout flow built on the Calibre platform. This core competency is what allows our manufacturing partners to assemble the fastest and the most accurate design-to-mask solutions (“An Integrated design-to-manufacturing flow for SADP”).

So if you are involved in design for manufacturing or post-tapeout engineering, come out to SPIE to see these papers and many more, from February 22-25 at the San Jose Convention Center. Mentor genius will be in available in presentations and at booth #225 to chat about any lithography-related issue on your mind.

Figure 1. Etch contour with multi-layer VEB model.



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