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Packaging Conference Addresses Challenges, Opportunities in New Technologies

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By Jeff Dorsch, Contributing Editor

On the second day of the 12th annual 3D ASIP conference, the heavy hitters came out to talk. Attendees heard presentations from executives of Amkor Technology, the Defense Advanced Research Projects Agency (DARPA), Northrop Grumman, Taiwan Semiconductor Manufacturing, Teledyne Scientific & Imaging, and Xilinx, among other companies.

The day began with Pioneer Awards presented to Mitsumasa Koyanagi of Tohoku University and Peter Ramm of Fraunhofer EMFT. Those two men then gave talks on their involvement in 3D packaging technology over the decades.

“It started with DRAM in 1974,” Koyanagi recalled.

Ramm reviewed various European initiatives in the field, including the development of InterChip Vias (ICVs), a precursor to through-silicon via (TSV) technology, and the concept of known good die.

Suresh Ramalingam of Xilinx discussed the attributes of Silicon-less Interconnect Technology (SLIT), which the chip company developed in cooperation with Siliconware Precision Industries (SPIL), the IC assembly, bumping, and testing contractor.

“It’s still a silicon platform,” he pointed out. SLIT promises to connect multiple die in a package without resorting to TSVs. “Wafer warpage is a big issue,” Ramalingam noted.

Amkor’s Mike Kelly followed Ramalingam. “There’s a kind of upturn or resurgence in 2.5D, driven by high-bandwidth memory,” he said.

Amkor is offering the Silicon-less Interposer Module (SLIM) as its TSV alternative technology, according to Kelly, while also providing Silicon Wafer Integrated Fan-out Technology (SWIFT) as another packaging alternative to TSV-based interconnections.

KC Yee of TSMC, filling in for an absent presenter, spoke at length about the foundry’s Integrated Fan-Out (InFO) wafer-level packaging technology. “InFO eliminates silicon, TSVs, interposers,” he said. At the same time, InFO “reduces cost,” he asserted.

DARPA’s Daniel Green spoke about the agency’s Diverse Accessible Heterogeneous Integration (DAHI) program, which succeeded its Compound Semiconductor Materials on Silicon (COSMOS) program.

He was followed by Augusto Gutierrez-Aitken of Northrop Grumman Aerospace Systems. “DAHI is not in competition with CMOS,” he said. NGAS is developing a foundry for heterogeneous integration projects, inviting in companies and universities to participate in the research and development.

Teledyne Scientific’s Miguel Urteaga spoke about his company’s CS-STACK 3D stacking chip program. “We’re looking to get the highest III-V performance we can,” he said.



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2 Responses to “Packaging Conference Addresses Challenges, Opportunities in New Technologies”

  1. dyi chung hu Says:

    You may miss mention the talk by Dyi Chung Hu, SiPlus/Unimicron. He mentioned the Integration of substrates, eHDF. It is an emerging TXVless, solder-less and underfill-less low cost system integration platform technology.

  2. Charlie Lu Says:

    The naming of recent developed packages/packaging technology is confusing.
    Two new terms were proposed to categorize those new packages, that’s ViB (Via-interconnect BGA) and FCrdlBGA. The idea was first presented in Semicon-Taiwan-2015 in September, and the Via-interconnect concept was demonstrated in the paper titled “A New Species of IC Package: Via-interconnect Ball-Grid-Array (ViB)” published in IMPACT-2015 conference. Go to Researchgate, search “Charlie Lu” you will find the details.

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