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3D ASIP Conference Hears from EDA, IC Gear Companies

By Jeff Dorsch, Contributing Editor

John Ferguson of Mentor Graphics provided the electronic design automation perspective on packaging technology at the 12th annual 3D ASIP conference in Redwood City, Calif.

“There’s a lot of interest and a lot of excitement about fan-out wafer-level packaging,” the director of marketing for Mentor’s Calibre DRC product line said, presenting “opportunities and challenges.”

The process of “bringing IC design and package design close together” presents many questions, Ferguson observed. Package design software usually runs on Windows, while EDA tools are on Linux, he noted. “It’s not so easy to mix and match them,” he said.

What manufacturing output to employ? GDSII, Gerber, or OBD++?

“Not all these things have answers yet,” Ferguson acknowledged. “The pieces are not all there yet. We’re partnering with several companies.”

Ferguson touted Mentor’s Xpedition Package Integrator suite for dealing with fan-out wafer-level packaging design. “It brings you across all the domains,” he said. The Mentor software will enable designers to “visualize it and optimize it,” he added.

The conference also heard from executives of three semiconductor equipment companies.

Markus Wimplinger, corporate technology development and intellectual property director at EV Group, spoke about temporary and permanent bonding in chip packaging, comparing chip-to-chip, chip-to-wafer, and wafer-to-wafer bonding.

Chip-to-chip and chip-to-wafer “are more flexible,” while wafer-to-wafer “has great promise,” he said.

David Butler, vice president of product management and marketing at SPTS Technologies, may have taken the prize for longest presentation title with “More Die, Stronger Die. Smaller, Thinner Packages Drives Die Singulation by Plasma Etch.”

“Saws damage die,” he said. “Plasma dicing is better.”

SPTS partnered with DISCO to develop effective die singulation through plasma dicing, according to Butler. “Plasma dicing provides about two times [improvement] in die strength for small die, thin die,” he said.

Rajiv Roy, vice president of business development and director of marketing for Rudolph Technologies, spoke about lithography and inspection requirements for fan-out wafer-level packaging, while touting the company’s experience in those areas.

Wafer and panel warpage can be a concern in FO-WLP manufacturing, he noted. “JetStep successfully measured and corrected for die placement errors,” Roy said, referring to Rudolph’s JetStep Advanced Packaging Lithography Systems, which can accommodate round or square/rectangular substrates.

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