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Conference Features “The Year of Stacked Memory” in 2015

By Jeff Dorsch, Contributing Editor

The theme of this year’s 3D Architectures for Semiconductor Integration and Packading (3D ASIP) conference is “The Year of Stacked Memory,” noting how memory die stacked in one package are becoming more commonplace in 2015.

Put on by RTI International, the 3D ASIP conference is in its 12th year. Attendees and presenters are generally people involved in chip packaging, from academia and industry.

One presentation on Wednesday (December 16) was by Teruo Hirayama of Sony, which has a long history of developing CMOS image sensors, dating back to 1998 with the graphics synthesizer for the PlayStation 2 video-game console, employing embedded DRAMs.

Embedded DRAMs present a number of manufacturing challenges, such as requiring four photomasks at the time, compared with three masks for commodity DRAMs and two or so masks for “pure logic” chips, Hirayama noted.

To address the issue, Sony turned to “chip-on-chip” technology, combining the merits of system-on-a-chip devices and system-in-package technology, according to Hirayama. The chipmaker later resorted to stacked CMOS image sensors, which offer a cost advantage over conventional CMOS image sensors.

During fiscal 2014, stacked CMOS image sensors accounted for 64 percent of Sony’s CMOS image sensor shipments, with back-illuminated image sensors representing 31 percent and front-illuminated image sensors 5 percent, Hirayama reported.

For future directions in stacked image sensors, Hirayama pointed to connecting pixels to analog-to-digital converters, with a device that has memory, a microelectromechanical system device, and a radio-frequency chip on the bottom layer, topped with a logic device, the ADC, and pixels, in that order.

The conference also heard Wednesday from Bryan Black of Advanced Micro Devices, a senior AMD fellow who spearheaded development of the company’s Fiji graphics processing unit.

The project started in 2007 and took 8.5 years to complete, Black said. “The industry needed a new memory system,” he commented. “We ended up with a die-stacking solution.”

Virtual prototyping was employed along the way, according to Black.

With a silicon interposer measuring 1,011 square millimeters and an ASIC coming in at 592 square millimeters, with four high-bandwidth memories, the Fiji GPU module is a big device. “We realized the part was going to be much bigger than we expected,” Black recalled. “Then we realized this thing would be huge.”

Wrapping up on Wednesday, the conference also heard presentations by three suppliers of semiconductor production equipment – EV GroupSPTS Technologies, and Rudolph Technologies.



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