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CMP Technology Evolving to Engineer Surfaces

By Ed Korczynski, Sr. Technical Editor

The 2015 International Conference on Planarization/CMP Technology (ICPT 2015) happens September 30 – October 2, 2015 in Arizona. As already reported online at Solid State Technology, ICPT 2015 is jointly hosted by the CMP User’s Group of the Northern California Chapter of the American Vacuum Society, Clarkson University Center for Advanced Materials Processing (CAMP), and the Institute of Electrical and Electronics Engineers (IEEE), and includes over 100 technical presentations and poster papers, with over 300 registered attendees at press time. In the lead up to this important gathering, SemiMD contacted the organizers and leading companies presenting to discuss how CMP is evolving to be able to provide atomic-scale surface engineering for future ICs.

Rob Rhoades is CTO of CMP technology provider Entrepix and co-chair of ICPT2015, and he sees broad themes of interest in industry today: unit-process extensions into new integration flows, and the need for CMP to enable new engineered substrates such as GaN-on-Silicon. “The substrate is branching out from just traditional silicon, but more importantly the layers grown on the substrate may be lattice-mismatched or strain-release layers. When you grow a lattice-mismatched layer it never grows smoothly, so when it comes out of the epi-growth chamber there’s need for a new CMP process.”

Growth in installed global capacity for "3D" finFETs for logic and V-NAND for Flash memory, resulting in significant demand for CMP processing. (Source: Applied Materials)

Figure 1: Growth in installed global capacity for "3D" finFETs for logic and V-NAND for Flash memory, resulting in significant demand for CMP processing. (Source: Applied Materials)

Figure 1 shows that much of the reason that the CMP market continues to grow is that 3D logic in the form of finFETs and 3D memory in the form of Vertical-NAND Flash (V-NAND) require many more CMP steps compared to planar IC processing. “Also, there’s a lot of interest in 3D integration using technologies such as TSV,” informed Rhoades. “Since there’s no industry standard on how to do TSV, and each company is developing processes that leverage their own technologies and tool-sets we’re still seeing a lot of development taking place, and there’s more than one path that looks possible.”
“Ten years ago, the goal from both fabs and suppliers was to get standard processes with wide windows. That goal has almost disappeared because the materials and the design-constraints are so tight that fabs want a unique slurry set for each unit-process. It’s a 180-degree reversal from where the industry was.”

Atomic-scale Surface Engineering

Just as there are changes in material properties when going from bulk to micron-scale “thin-films”, so too are there fundamental changes in material properties when going from thin-films to the atomic-scale. Surface inter-diffusions and other slight compositional variations begin to dominate properties, requiring additional control in the CMP process. “Some people are even ignoring the removal rate, and just specifying the process for end-point-control,” explained Rhoades. “If it takes 42 seconds or 47 seconds to clear it doesn’t matter, but the layer has to clear perfectly.”

Sidney Huey, global product manager in the CMP business group of Applied Materials, explained that the Front End Of Line (FEOL) forming 3D transistors needs CMP processes with atomic-scale control. “We internally talk about processes that are characterized by minimal material removal while controlling selectivities as ‘interface engineering’,” explained Huey, “There is a very clear trend toward use of interface engineering for the 3D nodes like 14/16nm. Customers are finding that to get these 3D devices to perform well and consistently they are having to re-examine many of the process parameters derived from planar nodes.” Since the “post-CMP-clean” process has traditionally been where final surface treatment is done, it is increasingly important to manage the  interdependent between CMP and clean.

Today’s Reflexion (R) LK Prime (TM) CMP tool can be extended with new pads and new slurries, but hardware designs will evolve to manage the selectivities of an increasingly broad materials set. “Our LK-Prime platform will address 14nm and 10nm nodes, but in the 7nm node with new interface engineering challenges we’ll likely need more innovation in hardware,” predicted Huey. “What we are asked to do is not just improve uniformity but to leave the surfaces as desired for the next process step.” While it may be too soon to be able to accurately predict how many new CMP unit-process steps will be needed as the industry transitions from 16/14nm-node to sub-10-nm-node logic flows, it is certain that some processes will have to clear topography with unprecedentedly low levels of dishing/erosion.

Industry collaboration needed

In the 2015 Entegris Yield Breakfast forum keynote address—held during SEMICON West in San Francisco this year—Dr. Archita Sengupta, Intel Technologist and Technical Supplier-related MCSC Program Manager, called for greater collaboration across the industry to control yield in advanced technology nodes. Figure 2 shows that the entire semiconductor ecosystem must work together to manage the increasing interdependency that comes with atomic-scale processing.

Figure 2: Due to inherent complexity in managing defects at advanced technology nodes, ever greater collaboration is needed throughout the industry ecosystem. (Source: Intel)

As the CMP process evolves to interface-engineering, the abrasive concentrations of slurries is lowered while abrasive sizes are smaller. With more chemical reactions and less mechanical force, unexpected zeta-potentials on surfaces and abrasives can result in agglomeration within the slurry such that slurry filtration strategy must be reconsidered. “As the sensitivity to wafer scratch defects continue to rise in the production of advanced integrated circuits, reductions in contamination levels are critical to improve yields,” reminded Entegris Vice-President of the Liquid Microcontamination Control business unit, Clint Haris. Entegris will tackle this complex topic at ICPT in the presentation, “Effects of Surface Zeta Potential on the Filtration Behavior of Colloidal Abrasives.” Entegris has expanded its CMP filtration technology portfolio for all three major contamination points (bulk chemical distribution, point of tool, and point of dispense) and will showcase these capabilities at the exhibit. Additional topics that Entegris likes to discuss include, “CMP Process Solutions through Optimized and Integrated Consumables” and “Efficient Development of Post-CMP Cleans for Ceria Slurries.”

Any surface-engineering processes control is additive to all the other process controls already needed in CMP processing. “If you want to control surfaces, you have to have the other aspects of the process under control,” Huey reminds us. “Even in R&D customers need the process to be as repeatable as possible so that they can figure out what’s going on.”

Pads and pad-conditioners will likely continue to be somewhat standard consumables, while at the leading-edge the slurries are becoming more single-source bespoke. Rhoades expounded upon the dynamic, “First of all the original supplier that dedicates thousands of hours of R&D to develop the product won’t give the IP to the 2nd-source. What this means is that the supply-chain management techniques have evolved, for example there may be need to keep more single-sourced materials on the shelf and limit just-in-time deliveries.” So the bad news is that an extended-shelf-life specification imposes yet another constraint on the R&D of slurries. The good news is that advanced slurry and filtration suppliers should expect healthy long-term partnerships with customers.



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