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Time to “shift left” in chip design and verification, Synopsys founder says

By Jeff Dorsch, contributing editor

The world is moving toward “Smart Everything,” according to Aart de Geus, founder, chairman, and co-CEO of Synopsys. “The door will open gradually, and then quickly,” he said in Tuesday’s keynote address at the Design and Verification Conference and Exhibition, or DVCon, in San Jose, Calif.

“The assisted brain is on the way,” de Geus told the standing-room-only audience. “This may be dreaming, but I don’t think so.”

Taking “Smart Design from Silicon to Software” as his official theme, the veteran executive urged attendees to “shift left” – in other words, “squeezing the schedule” to design, verify, debug, and manufacture semiconductors. “Schedules haven’t changed much,” de Geus said. The difference now is that the marketing department has as much influence in planning and scheduling a new product as the engineering department, he noted.

Chip designers also should “shift left” on semiconductor intellectual property, de Geus said. “IP reuse is the biggest change in 15 to 30 years,” he asserted. “Reuse leverages your innovation.”

After plugging the concepts of unified compilation and unified debugging architectures, de Geus touted the use of virtual prototypes in chip design. “Software guys are impatient with you,” he said. Synopsys, he noted, has created 400 million lines of software code.

Turning to the Internet of Things, de Geus said, “There are a lot of opportunities there.” The problem is “these things are full of cracks,” he added. There are significant engineering and security issues that must be addressed in networks of connected devices.

Developing the FinFET “was said to be impossible seven to eight years ago,” de Geus said. Nonetheless, the semiconductor industry was able to realize that advanced technology to move beyond the 28-nanometer process node, he noted. The future is likely to present similar challenges.



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