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Deeper Dive — Mentor Graphics Looks to the Future

Mentor Graphics is a survivor.

Established in 1981, the electronic design automation software and services company, based in Wilsonville, Ore., was once part of the “DMV” triumvirate in EDA. That acronym stood for Daisy Systems, Mentor Graphics, and Valid Logic Systems. Daisy and Valid are long gone, supplanted by Cadence Design Systems and Synopsys. Mentor abides.

Walden C. (Wally) Rhines has been Mentor’s chairman and chief executive officer since 2000, and before that served as the company’s president and CEO for seven years. His 21 years at Mentor now matches his 21 years at Texas Instruments, where he worked before joining Mentor.

For the fiscal year ended January 31, 2014, Mentor posted revenue of $1.156 billion and net income of $155.3 million. For the six months ended July 31, 2014, the company reported revenue of $512.4 million and net income of $11.6 million. System and software revenue accounted for nearly 64 percent of Mentor’s revenue in the past fiscal year, while service and support revenue represented 36 percent.

Like its main competitors, Cadence and Synopsys, Mentor Graphics is active in acquisitions. In late 2013, the company bought certain assets of Oasys Design Systems, the startup’s Oasys RealTime engine in particular. During fiscal 2014, Mentor acquired the assets of four privately-held companies for a total of $19.3 million. More recently, the company has acquired Berkeley Design Automation for nearly $47 million in cash, Nimbic, and XS Embedded.

The technical challenges of the semiconductor industry are the bread and butter of Mentor’s business, and it faces its own technical challenges in the nanoscale era of chip design and manufacturing. Mentor notes in its 10-K annual report, “Nanometer process geometries cause design challenges in the creation of ICs which are not present at larger geometries. As a result, nanometer process technologies, used to deliver the majority of today’s ICs, are the product of careful design and precision manufacturing. The increasing complexity and smaller size of designs have changed how those responsible for the physical layout of an IC design deliver their design to the IC manufacturer or foundry. In older technologies, this handoff was a relatively simple layout database check when the design went to manufacturing. Now it is a multi-step process where the layout database is checked and modified so the design can be manufactured with cost-effective yields of ICs.”

There has been a great deal of handwringing and naysaying about the industry’s progress to the 14/16-nanometer process node, along with wailing and gnashing of teeth about the slow progress of extreme-ultraviolet lithography, which was supposed to ease the production of 14nm or 16nm chips.

Joseph Sawicki, vice president and general manager of Mentor’s Design-to-Silicon Division, is having none of it.

Joe Sawicki

He recalls seeing a 1988 article about the impending doom of the chip business, faced with making IC features smaller than 1 micron. The submicron era didn’t destroy the semiconductor industry, of course. At the 130nm process node, there was serious discussion that it wouldn’t be necessary to progress to 90nm, which would be difficult or impossible to achieve, according to Sawicki. “Now, we’re hearing the same talk” in discussions about the forthcoming 10nm and 7nm process generations, he says.

In the past and at present, it’s necessary to maintain a spirit of “willful optimism,” Sawicki asserts. He points to Apple’s A8 processor, a custom chip inside the iPhone 6 and iPhone 6 Plus handsets, as an example of outstanding 20nm design that offers twice the density of its predecessors for Apple’s mobile devices.

What makes Sawicki optimistic about the current challenges is “this wonderful ecosystem, all the players, including EDA,” he says. “Scaling is not as easy,” he acknowledges. “It’s not nearly as bad as people are portraying it.” Mentor is working with such parties as imec, the University of Albany’s College of Nanoscale Science & Engineering, and the Semiconductor Research Corporation, according to Sawicki.

When it comes to fretful discussions of what will happen at 3nm and 5nm, Sawicki doesn’t see a reason to panic. “That’s three nodes out,” he notes. “Everything looks impossible.” Looking one node ahead, “we think we’re okay,” he adds.

The semiconductor industry, Sawicki says, has “a pretty clear path out there for the next six to 12 years. It really has to be willful optimism.”

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2 Responses to “Deeper Dive — Mentor Graphics Looks to the Future”

  1. Matt Says:

    Your caption for Joe should read Sawicki, FYi

  2. shannon Says:

    Thanks, Matt. This correction has been made. We apologize for the error.

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