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TSV Market Demand Now for Performance not Size


By Ed Korczynski, Sr. Technical Editor, SST/SemiMD

Through-Silicon Vias (TSV) have finally reached mainstream commercial use for 3D ICs, though still for “high-end” high-performance applications. Despite allowing for extreme miniaturization, the demand for TSV has little to do with package size as evidenced by recent Samsung and TSMC product announcements for “enterprise servers” and “routers and other networking equipment.”

Used to connect opposite sides of a silicon substrate to allow for stacking of multiple Integrated Circuit (IC) chips in a single functional package, the industry has been using TSV in Micro-Electro-Mechanical Systems (MEMS) and Backside Image Sensors (BSI) manufacturing for many years now. Also, the first announcement of a commercial FPGA product using TSV in a so-called “2.5D” interposer package happened four years ago.

(Source: Yole Devellopement)

However, the Figure above shows that CIS and MEMS and 2.5D-FPGAs can all be categorized as “niche” applications with limited growth potentials. Specialty memory and logic (and eventually photonics) applications have long been seen as the major drivers of future TSV demand.

On September 25 of this year, TSMC announced it has collaborated with HiSilicon Technologies Co, Ltd. to create an ARM-based networking processor that integrates a 16nm-node logic chips with a 28nm-node I/O chip using silicon interposer technology. This is the same 2.5D TSMC-branded Chip-on-Wafer-on-Substrate (CoWoS) technology used in the Xilinx FPGA product. “This networking processor’s performance increases by three fold compared with its previous generation,” said HiSilicon President Teresa He. Package size reduction has nothing to do with the value of the products now demanding TSV.

Samsung announced last August that it has started mass producing the industry’s first 64GB DDR4 registered dual Inline memory modules (RDIMMs) using TSV. Targeting enterprise servers and “cloud” data centers, the new RDIMMs include 36 DDR4 packages, each of which consists of four 4-gigabit (Gb) DDR4 DRAM dice. The low-power chips are manufactured using Samsung’s 20nm-node process. The company claims that the new 64GB TSV module performs twice as fast as a 64GB module that uses wire-bonding, while consuming about half the power. Samsung has invested in TSV R&D since 2010 for 40nm-node 8GB DRAM RDIMMs and 2011 for 30nm-node 32GB DRAM RDIMMs.

The Hybrid Memory Cube (HMC) and other heterogeneous 3D-IC stacks based on TSV should be seen as long-term strategic technologies. HMC R&D led by Micron continues to serve near-term customers demanding ultra-high performance such as supercomputers and performance networking, as detailed in an SST article from last year. Micron’s Scott Graham, General Manager, Hybrid Memory Cube, commented then, “As we move forward in time, we’ll see technology evolve as costs come down for TSVs and manufacturing technology, it will enter into future space where traditional DDR type of memory has resided. Beyond DDR4, we can certainly see this technology being for mainstream memory.”

Elusive Demand for Mobile Applications

14 years ago, this editor—while working for an early innovator in TSV technology—was co-author of a “3D stacked wafer-level packaging” feature article in SST.

The lead paragraph of that article summarizes the advantages of using TSV to reduce package sizes:

As electronics applications shrink in size, integrated circuit (IC) packaged devices must be reduced both in footprint and in thickness. The main motivation for the development of smaller packages is the demand for portable communications devices, such as memory cards, smart cards, cellular telephones, and portable computing and gaming devices. End-users of such electronic devices are interested in greater functionality per unit volume, not relatively simplistic metrics, such as transistors per chip or circuit speed.

While still true, established and inherently lower-cost packaging technologies have been extended to allow for stacking of thinned silicon chips:  wire-bonding can connect dozens of layers to a substrate, flip-chip with wire-bonding and substrate-vias can connect 4 layers easily, and both fan-in and fan-out packages can provide ample electrical Input/Output (I/O) connections. At SEMICON West this year in the annual Yield Forum breakfast sponsored by Entegris, Qualcomm vice president Dr. Geoffry Yu reminded attendees that, “TSV eventually will come, but the million dollar question is when. The market forces will dictate the answer.” What has become clear in the last year is that market demand for improved product performance will set the pace.


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One Response to “TSV Market Demand Now for Performance not Size”

  1. Mike Clayton Says:

    Very timely overview of TSV evolution and wafer level packaging. We have been INTEGRATING circuits ever since the military started funding “batch electronics” for the first IC fabs in 1959-62 period when the name went from batch electronics to and molecular electronics and solid circuits to integrated circuits the final name at that time that stuck. Hybrid circuits were what we called multi-chip and/or mixed technology packaging. Gradually the thick films disappeared as we learned to made better precision resistors and caps in silicon, and the ceramic substrate moved to their niche while plastics took over the consumer market and more over time. But with microcontrollers with 45 layers now, selling for a a buck or two, and memory chips pushing the bleeding edge, it seems that 3D has found its niche in furthering that Circuit Integration effort in typical “hybrid” fashion.

    Nobody ever got much market share in hybrid circuits, but they were used in everything from heart pacers to space systems. It was fast changing technology, competing with monolythic IC chips and single chip packaging. And as my old boss at Motorola said, “you should not build a business on a technology, build it on a customer needs.” – that was John Welty. But you have shown well the current niche and direction and the customer needs.

    Long ago, I was on a SemiCon West panel arguing for wire bonding with IBM defending flip chips, and ATT defending beam leads. I think wire bonding won, while the other methods evolved their niches based on performance and reliability rather than cost. But they are all still around, just without so much gold!

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