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SPIE Photomask Technology Wrap-up

Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.

Even with the wide variety of topics on offer at the Monterey Conference Center, many discussions circled back to EUV lithography. After years of its being hailed as the “magic bullet” in semiconductor manufacturing, industry executives and engineers are concerned that the technology will have a limited window of usefulness. Its continued delays have led some to write it off for the 10-nanometer and 7-nanometer process nodes.

EUV photomasks were the subject of three conference sessions and the focus of seven posters. There were four posters devoted to photomask inspection, an area of increasing concern as detecting and locating defects in a mask gets more difficult with existing technology.

The conference opened Tuesday, Sept. 16, with the keynote presentation by Martin van den Brink, the president and chief technology officer of ASML Holding. His talk, titled “Many Ways to Shrink: The Right Moves to 10 Nanometer and Beyond,” was clearly meant to provide some reassurance to the attendees that progress is being made with EUV.

He reported his company’s “30 percent improvement in overlay and focus” with its EUV systems in development. ASML has shipped six EUV systems to companies participating in the technology’s development (presumably including Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing, which have made equity investments in ASML), and it has five more being integrated at present, van den Brink said.

The light source being developed by ASML’s Cymer subsidiary has achieved an output of 77 watts, he said, and the company expects to raise that to 81 watts by the end of 2014. The key figure, however, remains 100 watts, which would enable the volume production of 1,000 wafers per day. No timeline on that goal was offered.

The ASML executive predicted that chips with 10nm features would mostly be fabricated with immersion lithography systems, with EUV handling the most critical layers. For 7nm chips, immersion lithography systems will need 34 steps to complete the patterning of the chip design, van den Brink said. At that process node, EUV will need only nine lithography steps to get the job done, he added.

Among other advances, EUV will require actinic mask inspection tools, according to van den Brink. Other speakers at the conference stressed this future requirement, while emphasizing that it is several years away in implementation.

Mask making is moving from detecting microscopic defects to an era of mesoscopic defects, according to Yalin Xiong of KLA-Tencor. Speaking during the “Mask Complexity: How to Solve the Issues?” panel discussion on Thursday, Sept. 18, Xiong said actinic mask inspection will be “available only later, and it’s going to be costly.” He predicted actinic tools will emerge by 2017 or 2018. “We think the right solution is the actinic solution,” Xiong concluded.

Peter Buck of Mentor Graphics, another panelist at the Sept. 18 session, said it was necessary to embrace mask complexity in the years to come. “Directed self-assembly has the same constraints as EUV and DUV (deep-ultraviolet),” he observed.

People in the semiconductor industry place high values on “good,” “fast,” and “cheap,” Buck noted. With the advent of EUV lithography and its accompanying challenges, one of those attributes will have to give way, he said, indicating cheapness was the likely victim.

Mask proximity correction (MPC) and Manhattanization will take on increasing importance, Buck predicted. “MPC methods can satisfy these complexities,” he said.

For all the concern about EUV and the ongoing work with that technology, the panelists looked ahead to the time when electron-beam lithography systems with multiple beams will become the litho workhorses of the future.

Mask-writing times were an issue touched upon by several panelists. Shusuke Yoshitake of NuFlare Technology reported hearing about a photomask design that took 60 hours to write. An extreme example, to be sure, but next-generation multi-beam mask writers will help on that front, he said.

Daniel Chalom of IMS Nanofabrication said that with 20nm chips, the current challenge is reduce mask-writing times to less than 15 hours.

In short, presenters at the SPIE conference were optimistic and positive about facing the many challenges in photomask design, manufacturing, inspection, metrology, and use. They are confident that the technical hurdles can be overcome in time, as they have in the past.

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One Response to “SPIE Photomask Technology Wrap-up”

  1. Diogenes Cicero Says:

    Several points from this article. First, the ASML paper was not about EUV progress but rather more EUV apologies, i.e. EUV “progress” is now measured in wafers per day. Remember when it was wafers per hour? Secondly, comparisons of EUV economies are now being made vs. octuple patterning. Meanwhile, ASML sells two (or 8??) 193i tools for every unsold, unprofitable EUV tools.

    Next, Peter Buck is correct about DSA. It’s simply the latest shiny penny which lithographers (particularly academic ones) take a liking to, because “its nice from far, but far from nice”. They’ve been doing it for 3 decades, in search of the Holy Grail NGL.

    Multiple beams will NOT “become the litho workhorses of the future”. It WILL become the mask makers workhorse of the future.

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