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Research Alert: June 17, 2014

Research on high-performance field-effect transistors to be presented at 2014 VLSI Symposium

A team of researchers from Purdue University, SEMATECH and SUNY College of Nanoscale Science and Engineering will present today at the 2014 Symposium on VLSI Technology on their work involving high-performance molybdenum disulfide (MoS2) field-effect transistors (FETs).

The team’s research is an important milestone for the realization of the ultra-scaled low-power 2D MoS2 FETs and the advancement of photonic and electronic devices based on transition metal dichalcogenide (TMD) materials such as solar cells, phototransistors and low-power logic FETs. The research is supported by Semiconductor Research Corporation (SRC), the world’s leading university-research consortium for semiconductors and related technologies, and SEMATECH.

As part of the research, the team leveraged MoS2, which has been studied closely in recent years by the semiconductor industry due to its potential applications in electrical and optical devices. However, high contact resistance value limits the device performance of MoS2 FETs significantly. One method to resolve this issue is to dope the MoS2 film, but doping the atomically thin film is nontrivial and requires a simple and reliable process technique. The technique used by the research team provides an effective and straightforward way to dope the MoS2 film with chloride-based chemical doping and significantly reduces the contact resistance.

“Compared with other chemical doping materials such as PEI (polyethylene imine) and potassium, our doping technology shows superior transistor performance including higher drive current, higher on/off current ratio and lower contact resistance,” said Professor Peide Ye, College of Engineering, Purdue University.

In order to obtain high-performance FETs, three parts of the device should be carefully engineered: semiconductor channel (carrier density and its mobility); semiconductor-oxide interface; and semiconductor-metal contact. This research is particularly aimed at eliminating the last major roadblock toward demonstration of high-performance MoS2 FETs, namely, high contact resistance.

The MoS2 FETs using the doping technique, which were fabricated at Purdue University, can be reproduced now in a semiconductor manufacturing environment and show the best electrical performance among all the reported TMD-based FETs. The contact resistance (0.5 kΩ·μm) with the doping technique is 10 times lower than the controlled samples. The drive current (460 μA/μm) is twice of the best value in previous literature.

“Due to recent advances such as the research being presented at the VLSI symposium, 2D materials are gaining a lot of attention in the semiconductor industry,” said Satyavolu Papa Rao, director of Process Technology at SEMATECH. “The collaborative effort among world-class researchers and engineers from this team is a prime example of how consortium-university-industry partnerships further enable the development of cutting-edge process techniques.”

“Improved contacts are always desirable for all electronic and optical devices,” said Kwok Ng, Senior Director of Device Sciences at SRC. “The doping technique presented by this research team provides a valid way to achieve low contact resistance for MoS2 as well as other TMD materials.”

UC Santa Barbara researchers introduce highest performing III-V metal-oxide semiconductor FET

Researchers from the University of California, Santa Barbara (UCSB) will introduce today the highest performing III-V metal-oxide semiconductor (MOS) field-effect transistors (FETs) at the 2014 Symposium on VLSI Technology.

The UCSB research promises to help deliver higher semiconductor performance at lower power consumption levels for next-generation, high-performance servers. The research is supported by the Semiconductor Research Corporation (SRC), the world’s leading university-research consortium for semiconductors and related technologies.

The UCSB team’s III-V MOSFETs, for the first time in the industry, exhibit on-current, off-current and operating voltage comparable to or exceeding production silicon devices — while being constructed at small dimensions relevant to the VLSI (very-large-scale integration) industry.

For the past decade, III-V MOSFETs have been widely studied by a large number of research groups, but no research group had reported a III-V MOSFET with a performance equal to, let alone surpassing, that of a silicon MOSFET of similar size. In particular, UCSB’s transistors possess 25 nanometer (nm) gate lengths, an on-current of 0.5mA and off-current of 100nA per micron of transistor width and require only 0.5 volt to operate.

“The goal in developing new transistors is to reach or beat performance goals while making the transistor smaller—it is no good getting high performance in a big transistor,” said Mark Rodwell, professor of Electrical and Computer Engineering, UCSB. “In time, the UCSB III-V MOSFET should perform significantly better than silicon FinFETs of equal size.”

To reach this breakthrough in performance, the UCSB team made three key improvements to the III-V MOSFET structure. First, the transistors use extremely thin semiconductor channels, some 2.5nm (17 atoms) thick, with the semiconductor being indium arsenide (InAs). Making such thin layers improves the on-current and reduces the off-current. These ultra-thin layers were developed by UCSB Ph.D student Cheng-Ying Huang under the guidance of Professor Arthur Gossard.

Next, the UCSB transistors use very-high-quality gate insulators, dielectrics between the gate electrode and the semiconductor. These layers are a stack of alumina (Al2O3, on InAs) and zirconia (ZrO2), and have a very high capacitance density. This means that when the transistor is turned on, a large density of electrons can be induced into the semiconductor channel. Development of these dielectric layers was led by UCSB Ph.D student Varista Chobpattana under the guidance of Professor Susanne Stemmer.

Third, the UCSB transistors use a vertical spacer layer design. This vertical spacer more smoothly distributes the field within the transistor, avoiding band-to-band tunneling. As with the very thin InAs channel design, the vertical spacer makes the leakage currents smaller, allowing the transistor’s off-current to rival that of silicon MOSFETs. The overall design, construction and testing of the transistor was led by UCSB Ph.D student Sanghoon Lee under Rodwell’s guidance.

“The UCSB team’s result goes a long way toward helping the industry address more efficient computing capabilities, with higher performance but lower voltage and energy consumption,” said Kwok Ng, Senior Director of Device Sciences at SRC. “This research is another critical step in helping ensure the continuation of Moore’s Law — the scaling of electronic components.”



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