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FinFET on SOI: Potential Becomes Reality

Authors: T. B. Hook, I. Ahsan, A. Kumar, K. McStay, E. Nowak, S. Saroop, C. Schiller, G. Starkey, IBM Semiconductor Research and Development Center

We report here empirical results demonstrating the electrical benefits of SOI-based FinFETs. There are benefits inherent in the elimination of dopant as the means to establish the effective device dimensions.  However, significant compromise is unavoidable when using doping as a means of isolation, as in bulk-based FinFETs.  Accordingly, we use SOI as the base on which to build the FinFET, which not only simplifies the process but enables full realization of the potential of the device.
Fully depleted transistor technologies – both planar and SOI-based FinFET – offer excellent circuit operation for SRAM and DRAM due to the unsurpassed threshold voltage matching associated with the near-absence of doping.   Additionally, good low voltage and stacked-fet circuit operation is realized due to the superior electrostatics associated with thin-body devices.  Hardware data specifically illustrating these features is described below.

Threshold voltage matching and distribution

A significant improvement in threshold voltage mismatch has been well documented, as well as the degradation associated with adding doping to a FinFET.  Less well publicized, however, is the even larger relative benefit to be found in thick-dielectric transistors, such as are used for analog and IO devices, and also in DRAM.

Random dopant fluctuation is not the only mechanism contributing to local threshold voltage mismatch, but it has historically been the largest contributor.  It has been an even larger contributor for thicker dielectrics, as its baleful influence scales directly with dielectric thickness, unlike work function variations for example.   Therefore an even more dramatic improvement in matching is found in thick-dielectric devices, as shown in Figure 1.

Figure 1. Mismatch data as a function of tinv for conventional doped (dotted line) and SOI FinFET (solid line). While the improvement in matching for ‘thin-oxide’ (1.2-1.5nm) is well known, less widely recognized is the even larger advantage obtained with ‘thick-oxide’ (>3nm) devices commonly used in IO and analog applications.

This improvement is important to IO and analog circuit operation and is vital to scaling the DRAM transfer device into the next generations.
In Figure 2 are shown probability plots of the threshold voltage for two DRAM transfer gate transistors and the profound improvement is obvious.   The FinFET version actually has a considerably thicker gate dielectric than the conventional doped device and a shorter gate yet much better matching.  The absence of thickness-driven matching opens up the device design space and enables optimization of the overall design, as well as allowing for the fundamental area scaling needed to move to the next generation.

Figure 2: Threshold voltage matching for DRAM transfer devices. Blue: 32nm generation thick oxide doping-controlled device. Red: 14nm generation thick oxide FinFET device. The FinFET device is shorter and has a thicker dielectric, yet the threshold voltage matching standard deviation is 0.7X that of the conventional planar doped version. This improvement is applicable also to other thick oxide devices, such as are used in IO and analog applications.

SRAM Vmin
One of the most important benefits of improved matching is the much-desired reduction in the minimum operating voltage of the classic 6T SRAM.  While the transistor matching data clearly show an advantage, putting it all together into a quantized FinFET SRAM cell with correct beta and gamma ratios and device centering to actually achieve low Vmin is a larger challenge.
Additionally, there may be other factors present in the scaled-up SRAM array that may not be so evident in the classic Pelgrom analysis from which most matching data are derived, such as some perturbation to line-edge-roughness, or nfet/pfet interactions, or any number of other possibilities.

Our data demonstrate that these concerns are surmountable and that real SOI FinFET SRAMs can operate at very low voltages. Figure 3 shows remarkable results on an SRAM array, with full read and write operation down to 400mV, without any assist circuitry.  This is among the best results ever reported, even among those that utilize boost techniques and in-situ tuning of the devices.

Figure 3: Shmoo plot of 14nm SOI FinFET SRAM array showing a minimum operating voltage of 400mV, with full read and write capability. This result, as good or better than any yet reported, was obtained without benefit of the chip-specific tuning techniques associated with planar fully depleted devices or specialized independent double-gate FinFETs.

Low Voltage Circuit Operation
A considerable improvement in electrostatics associated with the FinFET over conventional doped devices not only enables the necessary gate-length scaling, but simultaneously improves the relative performance at reduced voltage and therefore reduces the power density at a given performance.  While fully-depleted devices should in principle enjoy this advantage, the introduction of non-uniformity such as is involved with the tapered fin profile associated with bulk-based FinFET seriously compromises the output conductance and may obviate these expectations, as shown in Figure 4.

Figure 4: Representative bulk-based and SOI-based fin profiles, and corresponding empirical degradation in electrostatics. The tapered shape of the bulk fin shown results in nonuniform current flow and poorer low-voltage operation and self-gain than the more ideally shaped SOI FinFET.

The fin profile obtainable in SOI-based FinFETs is very nearly ideal and our data show that the low voltage benefits are fully realized in hardware.  The frequencies of a suite of ring oscillator circuits (inverter, NANDs, and NORs) were measured on 14nm SOI-based FinFET hardware as a function of voltage and compared to the modeled expectations.
Figure 5 shows excellent correspondence with expectation, and also shows how the data are far superior to the voltage dependence of conventional planar technology.

Figure 5: Normalized frequency reduction as a function of Vdd for a suite of circuits (NANDs, NORs, and inverters). Near-perfect correspondence of the SOI FinFET data with the compact model is shown. This flatter voltage dependence is highly superior to that typical of doping-controlled planar technology.

Conclusion
Several key elements of the putative advantages of FinFETs over conventional devices have been demonstrated in hardware.  By using SOI-based FinFET technology, the need for doping in the body has been effectively minimized, resulting in excellent matching characteristics in the undoped DRAM transfer device, and truly remarkable minimum operating voltage in the SRAM.  Additionally, the superior voltage dependence and stacked-fet circuit behavior relative to conventional devices has also been demonstrated through measurements of ring oscillators of various sorts.

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5 Responses to “FinFET on SOI: Potential Becomes Reality”

  1. Sang Kim Says:

    TSMC presented its first 16nm bulk Si based FinFET at 12/2013 IEDM that I attended. TSMC said it is in high volume manufacturing today. Therefore, Intel is not the only one. I am in general agreement with IBM’s empirical assessments of the electrical benefits of SOI-based FinFET. However, I would like to point out what is not addressed by IBM. In my opinion SOI based-FinFET has following two detrimental effects: floating body and self-heating effects. Some of hot electrons or hot holes generated by the high drain field could be trapped at SOI interface, resulting in transistor Vt shift. Similarly, SOI based-FinFET becomes more susceptible to Vt shift under cosmic rays and radiation exposure. As shown in Fig. 4, SOI-FinFET is almost completely dielectric-isolated, resulting in self-heating. Thus, Electrical transfer characteristics of SOI-FinFET including transistor breakdown voltages such as source/drain and gate will degrade due to self-heating with possible exception of hot carrier effect. As for differences between junction isolated Fin and dielectric-isolated Fin profiles, Intel presented it’s 22nm FinFET at 12/2012 IEDM (see paper 3.1.1). Intel showed two Fin profiles; one for low power and low voltage as shown here in Fig. 4 and another for high power for high voltage I/O transistors over 3V. Its Fin profile looks very much the same as the dielectric-isolated Fin profile as shown here in Fig. 4 although it is junction isolated. Lastly, the cost issue with Soitec SOI wafers has to be considered. Intel’s bulk based FinFET does not rely on Soitec SOI wafers. Also, what Soitec can deliver today in manufacturing is limited to 12nm SOI and 125nm BOX thickness. Intel’s 22nm FinFET is in high volume manufacturing over two years and its 14nm FinFET will be manufactured in the first quarter of 2014. Skim

  2. Xavier Says:

    Dear Skim,
    As you rightly point out, despite the benefits of SOI for FinFET described by IBM, some aspects are not addressed in this particular article — and TSMC’s as well as Intel’s works on FinFET are indeed impressive.
    However, I believe most of the concerns you raise regarding FinFET on SOI have been addressed in earlier workshops and publications. One of them is an article by the same Terry Hook in Advanced Substrates News, 18.Apr.2013 (http://www.advancedsubstratenews.com/2013/04/ibm-finfet-isolation-considerations-and-ramifications-bulk-vs-soi/).

    Not being a device specialist, I will mostly quote what the IBM author and device expert said there — my understanding of it anyway, hopefully it will make sense to you.
    Taking the concerns in order, what I gather from this reference is:
    1- Floating Body – is not a concern for Fully-Depleted device architectures, FinFET being one. Quoting Terry Hook: “In fully-depleted devices the concept of a floating body (charge storage in an isolated neutral region) is not applicable, so SOI and bulk FinFETs behave the same way for all switching scenarios.”
    2- Self-heating – exists for any thin body device, especially non-planar — be it bulk or SOI. The difference between SOI and bulk in that respect appears to be marginal, with the surface that is in contact with the buried oxide being small compared to overall fin surface. According to Terry : ” (…) bulk and SOI FinFETs have very similar self-heating characteristics, as the only difference in thermal conductance is a tall, thin sliver of silicon, which provides only a small increase in thermal conductance.”
    3- Sensitivity to cosmic rays and radiations – I was under the opposite impression, with SOI being less disturbed in that respect ? — based for example on the conclusions of IEEE paper “Comparing Single Event Upset sensitivity of bulk vs. SOI based FinFET SRAM cells using TCAD simulations ​”​, D.R.Ball et al in Proceedins of the SOI Conference 2012, quoted by IBM during various workshops.
    4- Fin Profile – I believe IBM was referring to having a less tapered fin profile in transistors used for logic and SRAM, which are those that matter for overall power/performance, much more than I/O transistors and the likes.
    5- Cost – an SOI starting wafer obviously is more expensive than a bulk wafer. On the other hand, since it “pre-defines” the fin height and has built-in isolation, it makes the CMOS fabrication process simpler. Therefore the yielded wafer cost is not necessarily higher and may actually be lower. You may want to check Terry’s statements in the comments section of the ASN article where, although he by no means pretends to be the right guy to make definitive statements on cost, he provides some interesting indications — one being: “Don’t presume that proper isolation is just a couple of block masks and implants. If one then quantifies the cost in terms of yield loss from variability, and the cost in terms of lost performance from the non-optimum transistor design point, then paying more for the starting substrate starts to look like a bargain.”
    6- Wafer availability – the 12nm silicon-thickness SOI starting wafer(with 25nm BOX, actually) is what Soitec delivers for planar FD-SOI technology at the 28nm node, not for FinFET (full disclosure: I work for them). Wafers with different top silicon and BOX thickness, perfectly suited to FinFET devices and actually specified with inputs from manufacturing partners, are also readily available and ship routinely to Soitec’s customers.
    Xavier.

  3. Terence Hook Says:

    Thank you for reading my article, and commenting thoughtfully. I must disagree with most of your observations, however. Self-heating and floating-body effects have been well known in PDSOI for many years and are largely immaterial, affecting neither reliability nor limiting circuit design. These concerns are of even less relevance to FinFETs, as bulk and SOI differ little with regard to either. By definition, in a fully depleted transistor, the ‘body’ is ‘floating.’ Even in a bulk FinFET the thin body potential is not established by the substrate potential. As for self-heating, there is a growing volume of literature that shows little difference in heating between dielectric-isolated and bulk transistors, perhaps most notably a paper from Intel (Trans. on ED 59(5) May 2012). We should all be pleased that self-heating is so well-understood, because we will all have to deal with it, bulk and SOI alike.

    I would agree that the high-voltage fin profile in that paper is better than the low-voltage profile, but it is still severely degraded from what we have shown for SOI fins. The fin width at the bottom is perhaps twice that of the top, while it is closer to three times wider for the thin oxide device. I would also note that the electrostatic control of the thick oxide device is almost entirely irrelevant, so even the marginal improvement illustrated in the TEM is of no real importance.

    With respect to cost I would be pleased to see an analysis of final die cost which proves that a bulk solution is less expensive than an SOI solution. The fin formation process is much more complex in bulk, with many more steps required. I have seen many analyses from many sources and there is virtually no difference in total processing cost.

    Perhaps just one comment on the TSMC bulk FinFET paper – they cite between 24 and 36% improvement in matching relative to their 28nm planar technology. There is published SOI data showing matching improvement of more than 65% in SOI finfets over an equivalent bulk planar design point. The use of ‘arbitrary units’ in those plots is truly puzzling to me, as real numbers for mismatch in SOI FinFETs and FDSOI fets have been extensively published. I am compelled to draw the conclusion that the actual results are distinctly disappointing.

    Finally, I am puzzled by the comment about Soitec and their capabilities. It is simply not true that only 125nm BOX is available (and so what if it were?) and 12nm thick silicon is not relevant for SOI FinFETs in any case. Also, while I am not an expert in wafer supply it is my understanding that appropriate wafers are available from all major manufacturers

  4. Sang Kim Says:

    Before my comment I would like to correct my typo error 125nm to 25nm BOX thickness. This is what I read IBM’s FDSOI roadmap published early this year by Horascio Mendes, executive director of the SOI Consortium. Skipping 22nm, he showed that 14nm FDSOI would be offered at the same time as Intel’s 14nm FinFET. For the 10nm node Horascio says IBM will offer both 10nm FDSOI and 10nm FinFET. I asked why both? Does IBM has a new road map now? According to analysis of Xavier and T. Hook here IBM seems to have no technological and manufacturing issues for SOI based FinFETs since no problems with floating body, self-heating, cosmic rays, wafer cost …etc.. Then what keeps IBM from manufacturing its SOI based FinFETs today? IBM skipped 22nm, 16nm and possibly also 14nm because Intel announced its 14nm FinFET would be manufactured in the first quarter of 2014. At what technology node the SOI based FinFET will be manufactured, at 10nm node? Xavier Cauchy also wrote an EDN article entitled ” Fully depleted silicon technology to underlie energy-efficient designs at 28nm and beyond” February 20, 2013. I wrote two comments in that article. Please read specially my last comment that reveals my prediction. You see Michigan that is Sang kim as designated by EDN.

  5. Ali Says:

    Dear Sang. I think you are mixing two different technologies here. The above article is IBM’s FinFET on SOI, which is IBM’s 14nm technology for its own products. IBM’s 22nm technology is PDSOI as presented at IEDM 2012. There is no node skipping here.

    Foundries on the other hand decided to put bulk FinFET in 20nm groundrule and call it 14/16nm.

    I parallel, IBM with its partners has developed the planar FDSOI technology (on thin BOX ~25nm). The technology is now available at 28nm. The next node, which is probably what Horacio showed, was renamed 14nm after foundries decided to call a 20nm-GR technology with advanced devices 14nm. This is a naming only and ground rules are same as what foundry calls 14/16nm.

    While it might look like as if there are two roadmaps, this is nothing new. This is very similar to what IBM used to do in earlier nodes: developing a PDSOI technology for IBM servers and some of the partners and a bulk technology for other partners.

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