What Will Replace Dual Damascene?
By Mark LaPedus
In the mid-1990s, IBM announced the world’s first devices using a copper dual damascene process. At the time, the dual damascene manufacturing process was hailed as a major breakthrough. The new copper process enabled IC makers to scale the tiny interconnects in a device, as the previous material, aluminum, faced some major limitations.
Dual damascene remains the workhorse process flow in the fab since its fabled introduction. But more recently, there are questions regarding the extendibility of the trusty dual damascene flow as the IC industry moves towards the 14nm node and beyond.
It all boils down to the interconnect. Copper interconnects—the tiny wiring schemes in devices—are becoming more compact at each node, causing an alarming increase in the resistance-capacitance (RC) delay. “The interconnect scaling roadmap looks like a looming disaster,” said Rob Aitken, an ARM fellow. “We want the materials to save us.”
The problem is that the dual damascene flow may extend to 10nm—and then could promptly run out of steam, according to some experts. Then, at 7nm, the industry may need to switch gears and move to a new flow—the single damascene process.
At 5nm, chip makers may need to switch again and re-visit the subtractive reactive ion etch (RIE) process for copper. Ironically, the industry explored the development of subtractive copper etch a decade ago, but the technology never got off the ground and was shelved.
Still others believe the risk-averse industry would rather extend the current technology as long as possible before moving to a new process. “I think dual damascene will extend to 10nm and probably the 7nm node,” said Daniel Edelstein, a fellow and manager of BEOL technology strategy at IBM. Edelstein was also the original project leader for IBM’s groundbreaking dual damascene efforts in the 1990s.
“I regard single damascene as a backup, not a front-up roadmap point,” he said. “Copper RIE is just one component of a subtractively etched multilevel copper wire and via integration, which I think is unworkable for copper.”
Beyond 7nm, the industry is looking at dual damascene, single damascene and copper RIE. In parallel, the industry is taking a different approach to the RC problem by working on stacked 2.5D and 3D chips. And for the distant future, the industry is looking at new transistor schemes, photonics and other technologies.
The looming crisis
For years, the industry has been grappling with a crisis in the interconnect. The industry averted a disaster in 1997, when IBM rolled out its CMOS 7S process, a 0.22-micron technology using the industry’s first dual damascene flow.
Until then, leading-edge logic devices deployed aluminum interconnects using an aluminum subtractive etch process. But as the industry moved towards 0.25-micron geometries and beyond, aluminum was unable to withstand the higher current densities in logic. And copper was (and still is) about 40% less resistive than aluminum, and it is less vulnerable to electromigration.
More recently, DRAM makers have made the transition from aluminum to copper. The shift towards copper requires a dual damascene process, which takes place at the back-end-of-the-line (BEOL) in the manufacturing flow. The process enables the formation of two main parts of the interconnect: metallization and low-k dielectrics.
In the dual damascene process, a structure undergoes a diffusion barrier etch step. Then, a via dielectric is deposited. An etch step then forms a gap, where the lines and vias are formed.
Then, a thin layer of barrier of tantalum (Ta) and tantalum nitride (TaN) materials are deposited using physical vapor deposition (PVD). Ta is used to form the liner and TaN is for the barrier in a structure. The barrier layer is coated over by a copper seed barrier via PVD. And finally, the structure is electroplated with copper and ground flat using chemical mechanical polishing (CMP).
In the single damascene process, the trenches and vias are formed one step at a time. In contrast, they are formed simultaneously in dual damascene. Fewer steps make dual damascene a less expensive approach. And in a completely different flow, the copper subtractive process makes use of RIE tools.
Dual damascene, meanwhile, continues to extend and evolve. PVD, the workhorse tool technology for the metallization process in dual damascene, may extend to at least 10nm. But if PVD should stumble, the industry is evaluating rival tool technologies like chemical-vapor deposition (CVD) and atomic-layer deposition (ALD).
In the low-k part of the equation, however, the technology remains stuck. “The RC delay is increasing,” said Dean Freeman, an analyst with Gartner. “To improve the RC delay, you need lower k materials. But to get lower k, you need to add more porosity or air to the dielectric material. That compromises the structural integrity of the dielectric. It also makes it more difficult to keep the copper from diffusing into the dielectric and causing shorts, or leakage between metal lines.”
There are also challenges in the metallization process. “The resistance of the copper is also increasing. As you get smaller and smaller vias and lines, you get smaller and smaller grains. A smaller grain/crystal means that you have more electron scatter, which increases the resistance and the heat in the device. This is why the device manufacturers are trying to keep the metal lines as wide as possible where they can,” Freeman said.
At 14nm, in fact, the interconnect is headed toward an “inflection point,” in which copper resistivity increases exponentially, said Mehul Naik, a distinguished member of the technical staff at Applied Materials.
“The question is how long you can extend copper damascene,” Naik said. “From a resistive perspective, how can you get more and more copper inside the trenches and how can you design your materials so you get rid of scattering issues that increase the copper resistivity. It’s maximizing the volume and minimizing the scattering of copper. If we can achieve that, we can extend damascene as far as possible. But that goes back into how you pattern the copper and get the fine pitch, and what kinds of issues you run into when you get a fine pitch.”
If dual damascene runs out of steam, the industry is looking at single damascene technology and subtractive copper etch. In theory, the single damascene approach could potentially enable smaller gaps with higher aspect ratios, but it is more expensive, Naik said.
Unlike single damascene, which may use existing tool technologies and materials, the industry may need to start from scratch in subtractive copper etch. “There are no tools (in the market),” he said. “So, you would need to develop a copper etch process.”
What’s next?
Looking into his crystal ball, IBM’s Edelstein sees dual damascene extending to at least 7nm and predicts a cloudy future for copper RIE. “Single damascene would be the backup with penalties if dual damascene breaks irreparably,” he said.
“Copper RIE discussions always seem to neglect the classic copper integration problems that would come with it. These problems were circumvented by going to damascene in the first place,” he said. “Why would bringing those unsolved problems back be any easier at vastly smaller dimensions? How would you propose to make a viable subtractive-etched multilevel copper BEOL line/via integration at competitive pitches, with all the needs for copper passivation, via contact, electrical and corrosion insulation, while at the same time retaining competitive cost, performance and reliability?”
Beyond 7nm, there are new and conventional approaches on the table. Even before 7nm, the industry is developing 2.5D/3D stacked chips to circumvent the RC delay problem. But advanced chip stacking has a number of challenges and is still a few years away from mass production
There are other and more futuristic technologies in R&D, many of which are exotic and expensive. The candidates include carbon nanotubes contacts, graphene, photonics, network-on-a-chip architectures, smart interconnects and others, said Jon Candelaria director of interconnect and packaging sciences at the Semiconductor Research Corp. (SRC).
For example, using a single damascene process, IMEC, TEL and others recently described 150nm diameter contacts filled with carbon nanotubes and a copper top metal. Carbon nanotubes before metallization reduced the single contact hole resistance from 4.8 kΩ down to 2.8 kΩ.
In a separate effort, Japan’s AIST recently fabricated multi-layer graphene interconnects directly on silicon dioxide by annealing sputtered amorphous carbon with a cobalt catalyst layer. A resistivity of around 500 μΩcm was obtained after cobalt removal.
And for years, the industry has been talking about the use of optical interconnects. “The bottom line is that the RC delay is increasing and there are no great solutions on the horizon other than copper and low-k,” said Gartner’s Freeman. “Ideally, the industry would like to go to a material with lower resistance, such as gold or carbon nanotubes for the interconnect. Unfortunately, gold is a bit too expensive and does not provide significant improvement over copper.”
Graphene is also expensive and involves some tough integration problems. “While nanotubes have demonstrated great promise, they have high resistance where they make contact to the metal lines. But IMEC has suggested that we are further along than people think on this topic,” Freeman said. “Optical interconnects are still a ways out. The big issue here is creating the laser and the collector in silicon, or on silicon. Intel continues to research this and I think they are getting close on chip-to-chip, but we are still a ways away from the technology.”
Tags: 10nm, 7nm, Applied Materials, ARM, damascene, Gartner, IBM, Imec, interconnects, low-k, nanotubes, Semiconductor Research Corp., TEL
January 25th, 2013 at 12:47 pm
As Freeman of Gartner pointed out, the RC delay problem is significant already at 22nm. Without solving this issue for now and an immediate next node, we cannot make profit for now and in the near future.
I think the high R is caused by the thick Ta barrier at the via bottom since it is connected in series, not in parallel like sidewall barrier; refer to published photos of Intel’s 22nm interconnect. By using 1nm thick PEALD TaNC, we can solve this increasing R problem. We can put PVD Ta over it as needed, and remove this Ta away at the via bottom since the PE-ALD TaNC can protect features from any heavy ion bombardment applied when removing the Ta at the via bottom.
The high C problem is caused by a smaller line-to-line distance than what we want to have since we cannot shrink the line and via CDs easily due to, for example, lithography difficulties; let’s confine our discussion to the cases that K value of ILD or IMD is identical among them. Here is the 3rd damascene process that can provide a method to decrease the line width with a retained sacrificial layer (S/L), as explained in US Patent 8,207,060. By decreasing the line width, the C can be decreased.
In the 3rd damascene process, a S/L comprising 1 or more sub-layers can be deposited over any damascene opening having any via opening (i.e., either via having via ESL remaining or that having no via ELS). This S/L is deposited to protect underlying damascene opening from the ion bombardment used to form a recess in the lower level conductor at the via bottom.
Let’s talk about a S/L consisting of 2 sub-layers of which 1st sub-layer is a conformal Low K dielectric layer so that we want to retain it after forming a recess in the lower level conductor at the via bottom. This layer is directly deposited over a damascene opening comprising Low K dielectrics. The 2nd sub-layer covering the 1st sub-layer can be of a very poor conformality of which it is thick on the field and the trench bottom, and thin on the via bottom. It is easy to make this conformality if CVD is used for 2nd sub-layer deposition. This 2nd sub-layer material must show a lot faster etch rate than the 1st sub-layer in a wet solution or in a gaseous etch chemistry that is used after the recess formation aforementioned. The finally retained 1st sub-layer comprising Low K dielectric material can now contribute to the decreased C for an increased distance between lines.
For a little more explanation of the 3rd damascene process, since the recess is formed in the lower level conductor before depositing a conductive liner layer comprising adhesion layer or metallic diffusion barrier layer or both is deposited, it does not damage the liner layer of important functions. Since even a conformal liner layer such as the PE-ALD TaNC can be used because it is deposited after the recess formation is completed, it is superior to the now-extinct punch-through damascene process that could not use any conformal barrier layer for the problems of trench bottom destruction and via merge occurring when forming the recess at the via bottom. This 3rd damascene process is superior to the now-dominant damascene process (i.e., a planar via damascene process) since it forms an embedded via in the lower level conductor, which is stronger than the planar via, and of a cleaner contact between the via and the conductor. Note that this embedded via is stronger and more electrically conducting than the planar counterpart in case a via is unlanded.
Only a tiny bit more investment is needed to implement this 3rd damascene process for forming the lower 3 to 5 levels of interconnects. Choosing a right combination of the sub-layers of the S/L and etching chemistry for removing the 2nd sub-layer of the S/L can be found through cooperation with MEMS engineers.