FinFETs or FD-SOI?
By Ed Sperling
STMicroelectronics yesterday unveiled the results of its 28nm production silicon chips using fully depleted silicon on insulator technology, which it claims offers a 30% improvement in speed over bulk CMOS while using less power.
The debate over FD-SOI and FinFETs has been notching up over the past few months. While FinFETs and FD-SOI both promise improvements in controlling leakage current, the FinFETs are more difficult to design. FD-SOI uses the same design flow, although it does use a different SPICE model with better characteristics than the one used for bulk CMOS.
ST also used an ultra thin body and box (UTBB) and body biasing to boost performance, according to Joel Hartmann, the company’s executive vice president of front-end manufacturing and process R&D. Hartmann presented his results at an SOI Consortium-sponsored event at the IEDM show last night.
“We are using body bias to boost performance,” Hartmann said. “You can do that with FD-SOI. We also decreased the Vdd of the device by applying body biasing.”
What’s particularly attractive about FD-SOI is that is can be implemented at the 28nm node for a boost in performance and a reduction in power. The mainstream process node right now is 40nm. And while Intel introduced its version of a finFET transistor called Tri-Gate at 22nm, TSMC and GlobalFoundries plan to introduce it at the next node—whether that’s 16nm or 14nm. That leaves companies facing a big decision about whether to move all the way to 16/14nm to reap the lower leakage of finFETs, whether to move to 20nm on bulk, or whether to stay longer at 28nm with FD-SOI.
Hartmann said ST has seen improvements in analog running on FD-SOI, and for memory where the minimum voltage required is lower. He said ST’s road map calls for FD-SOI all the way down to 10nm, with voltages dropping from 0.9v at 28nm to 0.8v at 14nm and 0.7v at 10nm.
One of the sticking points in adopting FD-SOI has been market acceptance. Despite the promise of improved performance and/or lower power, bulk CMOS has been extended using a variety of techniques such as strain engineering and FD-SOI is considered more expensive. At 28nm and beyond, however, bulk has run out of steam, which is why Intel has opted for finFETs.
Still, FinFETs are more difficult to design and manufacture, and they potentially can add significantly to the cost of an SoC. FD-SOI, in contrast, uses the same design tools and reduces the number of masks and metal layers. ST is the first large fab-lite company to adopt FD-SOI and to move beyond just test chips. It remains to be seen which path the rest of the industry takes—and how quickly.
Tags: FD-SOI, FinFETs, IEDM, Intel, Soitec, STMicroelectronics, tri-gate