Changes Ahead
Semiconductor Manufacturing & Design talks with GlobalFoundries EVP Mike Noonen about future challenges in IC manufacturing, the future of stacked die and ecosystem challenges ahead.
Tags: GlobalFoundries
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Deep Insights for Chip Builders
The move to 450mm wafers is under way, but nagging questions about ROI remain.…
Between A Rock And A Hard Place
Placement-friendly DP-aware cell design can avoid problems later down the line.…
FinFET Isolation: Bulk vs. SOI
Guest blog by IBM: A look at process integration, device design, reliability, and product performance differences.…
The latest milestones and future trends for making MEMS a mainstream technology.…
Even ‘average’ is a good thing when it comes to wafer demand.…
The Sun Is Bright. Use More Of It.
Are there realistic opportunity for new technologies? Short answer: Yes.…
SPIE Advanced Lithography 2013 - day 4
The last day of the conference gave the tool updates. So how is EUV progressing?…
Lessons From Past Architecture Wars
Why was Intel so successful when its very capable rivals were not? And can it maintain its lead?…
Forecast to reach $3.5 billion in 2014, but number of device makers at leading edge is shrinking.…
There's More To EUV Than Source Power
With a more powerful source, lithographers can use less-sensitive resists that are less prone to pattern collapse.…
President Obama Visits Applied Materials
Tour grabs national headlines as President speaks out on jobs and manufacturing.…
Semiconductor Manufacturing & Design talks with GlobalFoundries EVP Mike Noonen about future challenges in IC manufacturing, the future of stacked die and ecosystem challenges ahead.
Tags: GlobalFoundries
This entry was posted on Wednesday, October 17th, 2012 at 4:55 pm and is filed under Podcasts Videos Webcasts, Technology Features. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.
FinFETs On SOI
What's changing at the leading edge of Moore's Law and why those changes are so important.
Following a disappointing period in the first quarter of this year, IHS plans to lower its chip forecast to 4.8% for 2013, down from 5.6% in the previous forecast.
Sales were down, but shift to 300mm wafers hit a record as chipmakers moved to latest processes.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.
Enabling 12 technology nodes in 12 years.
Best practices for tackling electrical, physical and manufacturing challenges.
Decreasing time to yield requires planning for what patterns to generate, what data to archive and hot to optimize your test program.
A look at how to reduce custom/AMS design cycle time while improving design quality with on-demand, in-design signoff-quality verification.
Double patterning marks a turning point in terms of lithography, variability and complexity.
A look at the challenges and various solutions using LELE at 20nm, including place and route effects, OPC and mask misalignment and image rounding.
Getting more functionality on the same die area using more and increasingly complex verification rules is getting more difficult. Here are some solutions.
At 15nm and beyond, printing of pitches of 64nm and below will be required, and for EUV to replace ArF multi-exposure approaches patterns will have to be printed in a single-exposure process.