http://semimd.com/blog/2012/09/10/experts-at-the-table-stacked-die-reality-check-3/ Deep Insights for Chip Builders Thu, 25 Apr 2013 16:16:36 +0000 hourly 1 http://wordpress.org/?v= http://semimd.com/blog/2012/09/10/experts-at-the-table-stacked-die-reality-check-3/#comment-30238 Dev Gupta Tue, 11 Sep 2012 16:17:26 +0000 http://semimd.com/?p=6915#comment-30238 2.5 D modules are merely updated versions of MCMs using Si - substrate that had been used by IBM in mainframes etc. many years ago. The major difference in 2.5 D today are the use of micro - bumps and substrates w/ TSVs & buried caps. But the design / business rationale still remain the same : partitioning a large chip with too many transistors into a number of chips so as to reduce yield loss while at the same time integrate them at the substrate level w/o too much of a penalty in inter - chip delays by using fine pitch / area - array / low - loss interconnects. But MCMs did not become widespread as Intel could afford to stay on Moores's law for CMOS single chip microprocessors ( always cheaper than MCMs if you have the volume ). Regardless of all the process development effort in Packaging, history might repeat itself for 2.5 D ( not to menton 3-D ) for high volume chips at least thru 14 nm. As to the feared "Memory Wall" there are now more elegant ways to increase bandwidth than drilling holes ( TSVs ) in semi - finished wafers. 2.5 D modules are merely updated versions of MCMs using Si – substrate that had been used by IBM in mainframes etc. many years ago. The major difference in 2.5 D today are the use of micro – bumps and substrates w/ TSVs & buried caps. But the design / business rationale still remain the same : partitioning a large chip with too many transistors into a number of chips so as to reduce yield loss while at the same time integrate them at the substrate level w/o too much of a penalty in inter – chip delays by using fine pitch / area – array / low – loss interconnects. But MCMs did not become widespread as Intel could afford to stay on Moores’s law for CMOS single chip microprocessors ( always cheaper than MCMs if you have the volume ). Regardless of all the process development effort in Packaging, history might repeat itself for 2.5 D ( not to menton 3-D ) for high volume chips at least thru 14 nm. As to the feared “Memory Wall” there are now more elegant ways to increase bandwidth than drilling holes ( TSVs ) in semi – finished wafers.

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