Comments on: Foundries Tip Hybrid FinFET Flows http://semimd.com/blog/2012/08/16/foundries-tip-hybrid-finfet-flows/ Deep Insights for Chip Builders Thu, 25 Apr 2013 16:16:36 +0000 hourly 1 http://wordpress.org/?v= By: The Chipguy http://semimd.com/blog/2012/08/16/foundries-tip-hybrid-finfet-flows/#comment-29620 The Chipguy Thu, 23 Aug 2012 13:16:32 +0000 http://semimd.com/?p=6702#comment-29620 Nice article, For bulk finfet, when I look at the poor subfin device in parallel with the top fin device, I think Patton/IBM is spot on. SOI is the correct direction. This is obvious and something I was even taught in graduate school. I would even wager that as some smaller node Intel will need to switch to SOI to fix all it's issues with bulk finfet Nice article,

For bulk finfet, when I look at the poor subfin device in parallel with the top fin device, I think Patton/IBM is spot on. SOI is the correct direction. This is obvious and something I was even taught in graduate school. I would even wager that as some smaller node Intel will need to switch to SOI to fix all it’s issues with bulk finfet

]]> By: Ali http://semimd.com/blog/2012/08/16/foundries-tip-hybrid-finfet-flows/#comment-29423 Ali Fri, 17 Aug 2012 05:08:22 +0000 http://semimd.com/?p=6702#comment-29423 The modular Fin is broken by definition. There is strong correlation between fin density (pitch) and metal pitch. At 22nm Intel used fin pitch of 60nm and metal pitch of 90nm, a gear ratio of 1.5. There is a reason for this: Use a fin density that is too much for your metal density and you waste power; use too little and you end up having not enough number of fins per logic cell. Once you accept that 14nm and 22nm need different fin spacing, you need to develop completely different processes. The modular Fin is broken by definition. There is strong correlation between fin density (pitch) and metal pitch. At 22nm Intel used fin pitch of 60nm and metal pitch of 90nm, a gear ratio of 1.5. There is a reason for this: Use a fin density that is too much for your metal density and you waste power; use too little and you end up having not enough number of fins per logic cell. Once you accept that 14nm and 22nm need different fin spacing, you need to develop completely different processes.

]]> By: The-Fabguy http://semimd.com/blog/2012/08/16/foundries-tip-hybrid-finfet-flows/#comment-29420 The-Fabguy Fri, 17 Aug 2012 03:52:39 +0000 http://semimd.com/?p=6702#comment-29420 After 20nm and 28nm .....these node names are confusion. I don't see the value in using 14nm in frontend with larger 20nm features in backend. Seems like a mismatch. The industry has never done something like this before. When I worked in a fab we bought the best stepper and printed the smallest feature we could for both the font end and backend. If the smallest feature we could print with the state of the art stepper was 130nm line and 130nm space, we called the node "130nm" After 20nm and 28nm …..these node names are confusion.

I don’t see the value in using 14nm in frontend with larger 20nm features in backend. Seems like a mismatch.

The industry has never done something like this before. When I worked in a fab we bought the best stepper and printed the smallest feature we could for both the font end and backend. If the smallest feature we could print with the state of the art stepper was 130nm line and 130nm space, we called the node “130nm”

]]> By: TomK http://semimd.com/blog/2012/08/16/foundries-tip-hybrid-finfet-flows/#comment-29415 TomK Thu, 16 Aug 2012 20:55:01 +0000 http://semimd.com/?p=6702#comment-29415 Mark, Nice write-up and topic. Looks like foundry roadmap might be bankrupt. 1. Foundry Finfet has 20nm front-end standard cell density so how is this called "14nm" 2. I don't get TSMC calling their finfet 16nm either when that has 20nm density. 3. Now take finfet at what ever you call it and offer 2 back-ends: "14" and "20" and different foundries doing it differently. When has the industry ever done that? My company can't afford to develop IP for two flavors like that for multi-source Continuing, now in the article I might even need to switch to SOI wafers (something the industry have avoided for a decade due to cost) to get Finfets to work. Is this what the end of Moore's law looks like? In this roadmap, I don't see cost dropping ~20% a year like past. Hopefully your readers can explan how this roadmap outlined in the article keeps industry on Moore's Law. Mark,

Nice write-up and topic.
Looks like foundry roadmap might be bankrupt.

1. Foundry Finfet has 20nm front-end standard cell density so how is this called “14nm”

2. I don’t get TSMC calling their finfet 16nm either when that has 20nm density.

3. Now take finfet at what ever you call it and offer 2 back-ends: “14″ and “20″ and different foundries doing it differently. When has the industry ever done that? My company can’t afford to develop IP for two flavors like that for multi-source

Continuing, now in the article I might even need to switch to SOI wafers (something the industry have avoided for a decade due to cost) to get Finfets to work.

Is this what the end of Moore’s law looks like? In this roadmap, I don’t see cost dropping ~20% a year like past.

Hopefully your readers can explan how this roadmap outlined in the article keeps industry on Moore’s Law.

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