Foundries Tip Hybrid FinFET Flows
By Mark LaPedus
The 14nm node represents an inflection point for leading-edge foundries.
The foundries hope to make a monumental shift from conventional planar transistors at 20nm to finFET structures at 14nm. And to accelerate their finFET efforts, leading-edge foundries are looking at hybrid integration schemes and “modular fin” strategies.
Using this approach, a foundry would devise a fin structure at the front-end with 14nm design rules. The fin structure itself is modular, meaning it can be plugged into a newly developed and corresponding 14nm back-end-of-line (BEOL) interconnect flow.
But by being modular, vendors also have the option to plug in the 14nm fin into an existing planar 20nm BEOL flow. This hybrid integration approach could enable a vendor to accelerate its finFET introduction date, but there are also some die-cost disadvantages.
“There are no challenges from a process point of view,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “What you are doing is taking a fin module and making it compatible at 14nm and 20nm.”
By going the modular fin route, foundries hope to provide fast and flexible solutions for customers. “It has to be competitive,” he said. Foundries appear to be taking a “modular fin” approach for good reason: They must speed up their finFET efforts to play catch up with Intel and satisfy increasing customer demand for the technology.
Challenges mount at 14nm
The foundries face some challenges to integrate “modular fins,” not to mention bringing up finFET structures in the first place. At 14nm, there are other manufacturing challenges, such as etch, deposition, inspection and lithography. The net result is that there must be a closer collaboration between foundries and customers. “The key is to have a tighter integration between product design and manufacturing,” Kengeri said.
Clearly, the leader in finFETs is Intel Corp., which is already using the technology for its microprocessors at 22nm. At that node, Intel is also providing foundry services to a limited set of fabless chip makers.
Right now, the foundries are still ramping up their 28nm processes, with planar at 20nm and finFETs at 14nm in the works. At 14nm, the industry is not banking on extreme ultraviolet (EUV) lithography. The EUV power source is simply not ready.
Instead, the industry is gearing up for 193nm immersion and multi-patterning. “If EUV was ready today, people would use it,” said David Hemker, chief technology officer in the corporate technology development group at Lam Research. “The industry is confident using double pattering.”
Beside lithography, there is another pressing issue for finFETs: variability. Intel proved that a chipmaker could ramp up finFETs using bulk CMOS technology. Attempting to follow Intel’s successful formula, the foundries have decided to extend bulk CMOS into the finFET era.
But because of fin height variability, there are fears that the foundries could struggle making bulk finFETs. “People are just waking up to this,” said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. The foundries should take a harder look at silicon-on-insulator (SOI) technology, which can reduce fin height variability, Patton said. And because there are fewer process steps with SOI-based finFETs, the traditional cost penalty associated with SOI disappears, he added.
The finFET transition also will cause a spike for process-control tools. Given the soaring costs of IC designs, there is little margin for error. It will become more critical to spot killer defects much earlier in the process.
One of the emerging areas in process control involves non-visual defects. Non-visual defects do not scatter light and are not detectable by current optical or e-beam inspection tools. “Up to 30% of yield loss in today’s fabs are not traceable to physical defects,” said Robert Newcomb, executive vice president at Qcept Technologies, a metrology tool vendor.
Non-visual defects are cropping up in some new and unforeseen areas in finFET designs. In development work for one customer, for example, Qcept’s tools detected horizontal defect patterns in the outer 20nm to 30nm of the wafer in a finFET design.
Get out the scorecards
And if that isn’t enough, chipmakers will need a scorecard just to keep track of the foundries and their latest finFET roadmaps. The nodes at which vendors will introduce finFETs are a bit misleading and don’t necessarily tell which company is ahead in the race.
For example, United Microelectronics Corp. (UMC) is rolling out finFETs at 20nm. UMC is marrying a 14nm front-end fin with a 20nm backend. Rival Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is talking about finFETs at the 16nm half-node. So far, Samsung is sticking to its plans to launch finFETs at 14nm.
GlobalFoundries, meanwhile, has devised a modular fin with 14nm front-end design rules, but it has not decided whether it will insert the structure to a 14nm or 20nm BEOL scheme. “We’ve been analyzing to see what is the right approach,” Kengeri said. “We may put it on 20nm. We may put it at 14nm. We may put it on both.”
In all cases, chipmakers still are able to devise new and innovative IC designs with finFETs. “To achieve this, there are many aspects of finFET technology,” he said. “Optimization and upfront planning are key. The ratio of contacted poly pitch, metal layers and fin pitch are critical. The choice of fin pitch will impact fin efficiency, resistance-capacitance, cost, process complexity, scalability and many other metrics. Therefore, it is important to architect the finFET process with a fin pitch optimal for both 20nm and 14nm and targeted for specific applications.”
Still, the modular fin strategy has some tradeoffs. The first option is to combine a 14nm front-end modular fin to a corresponding middle-of-the-line (MEOL) and BEOL flow at 14nm. The fin structure can be easily manufactured using 193nm immersion, multi-pattering and other steps.
The real challenge is to devise an entire new MEOL and BEOL infrastructure at 14nm, which could be an expensive proposition. Chip manufacturers could extend their existing physical vapor deposition (PVD) tools to devise the interconnect at 14nm. But for the capping layers, chipmakers may need to move to new deposition tools as well as materials like cobalt, said Sree Kesapragada, global product manager for metal deposition products at Applied Materials.
Until foundries bring up a new 14nm MEOL/BEOL flow, they may opt to go with the less expensive hybrid approach. This marries a 14nm fin with a 20nm planar MEOL/BEOL flow. The idea behind this approach is that foundries can leverage and use their existing and mature 20nm tools.
There are also some time-to-market and tool cost-of-ownership advantages with the hybrid approach. “There are some pros and cons,” Kengeri said. “You can bring up the technology faster.”
The disadvantage is that the die cost is roughly similar between a 20nm planar device and a hybrid 14nm/20nm finFET. “You don’t get the die cost advantage” of a homogenous 14nm finFET structure, he said. There also could be some integration challenges in terms of the different capacitances between the 14nm front-end fin and the 20nm planar BEOL. “It’s something you have to account for and model,” he said.
Tags: 14nm, 20nm, Applied Materials, BEOL, EUV, finFET, GlobalFoundries, IBM, Intel, Lam Research, MEOL, PVD, Qcept Technologies, SOI, TSMC, UMC
August 16th, 2012 at 1:55 pm
Mark,
Nice write-up and topic.
Looks like foundry roadmap might be bankrupt.
1. Foundry Finfet has 20nm front-end standard cell density so how is this called “14nm”
2. I don’t get TSMC calling their finfet 16nm either when that has 20nm density.
3. Now take finfet at what ever you call it and offer 2 back-ends: “14″ and “20″ and different foundries doing it differently. When has the industry ever done that? My company can’t afford to develop IP for two flavors like that for multi-source
Continuing, now in the article I might even need to switch to SOI wafers (something the industry have avoided for a decade due to cost) to get Finfets to work.
Is this what the end of Moore’s law looks like? In this roadmap, I don’t see cost dropping ~20% a year like past.
Hopefully your readers can explan how this roadmap outlined in the article keeps industry on Moore’s Law.
August 16th, 2012 at 8:52 pm
After 20nm and 28nm …..these node names are confusion.
I don’t see the value in using 14nm in frontend with larger 20nm features in backend. Seems like a mismatch.
The industry has never done something like this before. When I worked in a fab we bought the best stepper and printed the smallest feature we could for both the font end and backend. If the smallest feature we could print with the state of the art stepper was 130nm line and 130nm space, we called the node “130nm”
August 16th, 2012 at 10:08 pm
The modular Fin is broken by definition. There is strong correlation between fin density (pitch) and metal pitch. At 22nm Intel used fin pitch of 60nm and metal pitch of 90nm, a gear ratio of 1.5. There is a reason for this: Use a fin density that is too much for your metal density and you waste power; use too little and you end up having not enough number of fins per logic cell. Once you accept that 14nm and 22nm need different fin spacing, you need to develop completely different processes.
August 23rd, 2012 at 6:16 am
Nice article,
For bulk finfet, when I look at the poor subfin device in parallel with the top fin device, I think Patton/IBM is spot on. SOI is the correct direction. This is obvious and something I was even taught in graduate school. I would even wager that as some smaller node Intel will need to switch to SOI to fix all it’s issues with bulk finfet