Part of the  

Solid State Technology

  Network

About  |  Contact

Headlines

Headlines

Challenges For Patterning Process Models Applied To Large Scale

Full-chip patterning simulation has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasi-rigorous optical models and semi-empirical resist and etch process models. This paper will review the steady improvement in the predictive power and runtime performance of the patterning models used in full chip simulation tools, as well as the factors that ultimately limit the predictability of such models. In addition, this paper will outline the new process simulation challenges that emerge as the industry approaches sub-0.25 k1 patterning: improving accuracy and predictability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.

To download this white paper, click here.

Tags: , ,

Leave a Reply