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Deep Insights for Chip Builders
The move to 450mm wafers is under way, but nagging questions about ROI remain.…
Between A Rock And A Hard Place
Placement-friendly DP-aware cell design can avoid problems later down the line.…
FinFET Isolation: Bulk vs. SOI
Guest blog by IBM: A look at process integration, device design, reliability, and product performance differences.…
The latest milestones and future trends for making MEMS a mainstream technology.…
Even ‘average’ is a good thing when it comes to wafer demand.…
The Sun Is Bright. Use More Of It.
Are there realistic opportunity for new technologies? Short answer: Yes.…
SPIE Advanced Lithography 2013 - day 4
The last day of the conference gave the tool updates. So how is EUV progressing?…
Lessons From Past Architecture Wars
Why was Intel so successful when its very capable rivals were not? And can it maintain its lead?…
Forecast to reach $3.5 billion in 2014, but number of device makers at leading edge is shrinking.…
There's More To EUV Than Source Power
With a more powerful source, lithographers can use less-sensitive resists that are less prone to pattern collapse.…
President Obama Visits Applied Materials
Tour grabs national headlines as President speaks out on jobs and manufacturing.…
Semiconductor Manufacturing and Design talks with Paul Boudre, chief operating officer at Soitec, about FinFETs, industry inflection points, the end of life for planar transistors, bulk CMOS vs. SOI, the differences between fully depleted and partially depleted SOI, and the FD-SOI ecosystem.
Tags: CMOS, FD-SOI, FinFETs, partially depleted SOI, planar transistors, SOI, Soitec