SEMI’s 3DS-IC Committee recently approved its first standard.

Pending procedural review, the document will be published as SEMI 3D1 or “Terminology for Through Silicon Via Geometrical Metrology.” SEMI 3D1 will provide a starting point for standardization of geometrical metrology for selected dimensions of through-silicon-vias (TSVs).

Getting standards in place for 3D has been a huge challenge and roughly fall into three categories:

1. Manufacturing: Standards are needed for everything from TSVs and how to put die together. This area has seen concerted activity, and both foundries and OSATs report significant progress.
2. Ecosystem: While IDMs will pursue their own strategies and processes, fabless companies are working to minimize risk and establish business relationships to ensure that if known good die do not work in a stack, there are protocols for resolving problems.
3. Design: Standards in this area are premature because there is so little experience in actually designing stacked die—and even 2.5D interposer stacks—that standards bodies are only beginning to think about what can and should be standardized.

While there are significant reasons to begin stacking die—particularly in 2.5D configurations at 20nm to avoid the added cost of shrinking analog and double patterning—there are still widespread concerns about just how ready the ecosystem will be and what the cost comparisons are between planar and stacked die. So far, there is insufficient information from any sources because there has been so little activity other than test chips.

—Ed Sperling

Tags: 3D IC, metrology, SEMI, stacked die, Standards, through-silicon via, TSV

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