By David Lammers

The 2012 Symposia on VLSI Technology & Circuits, planned for mid-June in Honolulu, points to future directions in memory technology, including 3-D NAND, spin torque transfer MRAM, ferroelectric memories, and other emerging memory types.

Intel’s K. Zhang will give an invited paper on SRAMs using tri-gate transistors, scheduled for June 13th in the late morning.

A team from GlobalFoundries, the Fraunhofer Center of Nanoelectronic Technologies, and NaMLab GmbH will describe progress with ferroelectric materials for non-volatile memories which consume less power than other new memory types. The team has created the “most aggressively scaled” FeFETs using ferroelectric Si:HfO₂ in a 28 nm HKMG stack (TiN/Si:HfO₂;/SiO₂/Si).

Unlike the current-based STT-MRAM, RRAM, PCRAM and Flash technologies the ferroelectric approach is based on a field effect and consumes the lowest power during switching.  “Even though researched for several decades, the ferroelectric field effect transistor (FeFET) based on traditional perovskite-based ferroelectrics like PZT or SBT still has fundamental shortcomings. Its potential, however, remains unchallenged,” the authors said.

FeFETs utilizing perovskite-based ferroelectrics still face scalability and manufacturability issues, causing the team to “engineer ferroelectricity in the well-known and fully CMOS-compatible HfO2 based dielectrics.” The team achieved a two order of magnitude scaling gap compared with previous FeFETs, using a 28nm technology, achieving “excellent yield, fast switching, good retention and endurance.”

Vertical NAND Advances

Macronix International researchers said they have a 3D NAND design as amenable to scaling as 2D NAND cells, which could lead to a cost-competitive 3D architecture.

“Despite vertical stacking, the lateral scaling of 3D NAND flash is critically important because otherwise more than 16 stacking layers are needed to be cost competitive to 20nm 2D NAND,” the Macronix researchers claim.

The team will propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method.

The IDG SSL decoding method “provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND.”

The paper will describe a 37.5nm half-pitch 3D NAND, perhaps the first to achieve sub-50nm HP scaling. The “highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND,” they said.

Cost-competitive VCCPCM

Hitachi researchers will report on a 3-D NVM technology that uses a scalable phase-change material and polycrystalline-silicon diodes as selection devices to minimize the cell layout area. They will describe a scalable 3-D vertical chain-cell-type phase-change memory (VCCPCM) with 4F² polysilicon diodes, arguing that the device can reduce bit costs compared to flash memory.

3-D stacking of bit cells will be needed to achieve higher storage capacity per unit of layout area and hence a lower cost-per-bit, they said.

A paper from Tohoku University will describe a three-dimensionally stacked reconfigurable-logic chip with ultrafast (5-ns write speed) on-chip NVM, implemented with spin-transfer torque memory cells. The architecture will provide a faster way to load configuration data in many-core architectures, aimed at higher system performance.

The Tohoku paper is entitled “Ultrafast Parallel Reconfiguration of 3D-Stacked Reconfigurable Spin Logic Chip with On-chip SPRAM (SPin-transfer torque RAM),” from T. Tanaka, et al.

Hynix Semiconductor researchers will describe a new metal control gate last (MCGL) process for high performance DC-SF (dual control gate with surrounding floating gate) 3D NAND flash memory.

The MCGL process can realize a low resistive tungsten (W) metal word-line with high-k IPD, a low-damage tunnel oxide/IPD, and a “preferable” floating gate shape, the authors said.

A conventional bulk erase can be used, replacing the GIDL erase in the competing BiCS design, due to direct connection between channel poly and p-well by the channel contact holes. The authors said the DC-SF cell can be applied to multi-level cell 3D NAND memories with 256Gb/512Gb densities.

Samsung Electronics researchers will describe solutions to intrinsic fluctuations in vertical NAND flash memories using polysilicon for the channel material.

Two sources of intrinsic variation of the cell threshold voltage induced by polysilicon traps have been identified: random trap fluctuation (RTF) and random telegraph noise (RTN).

“We demonstrate that RTN is enhanced by the polysilicon material and an original model explains the asymmetric RTN distribution observed after endurance. This work enables the prediction of VT distribution for VNAND devices in MLC operation,” the Samsung authors said in the paper’s abstract.

STT-MRAMs Beyond 20nm

Samsung Electronics researchers report the scalability of STT-MRAM cells beyond the 20nm generation. The approach uses perpendicular magnetization induced from the interface of free layer (FL) and the MgO tunnel barrier.

“We demonstrate that the MTJs utilizing dual interfaces of FL and MgO exhibit enhanced scalability with high thermal stability and low switching current, compared with the MTJs with a single interface,” the Samsung paper abstract reported.

Conductive Bridge RAMs

The symposium includes two full sessions on resistive RAMs (ReRAMs).

An Imec-led team will describe a conductive bridge random access memory (CBRAM) capable of field-driven sub-nanosecond programming. The team optimized a 90nm-wide CuTe-based 1T1R CBRAM cell aimed at ultrafast programming. They engineered an Al₂O₃ electrolyte and Ti buffer layers, demonstrating that switching is mainly controlled by field-driven motion of the Cu+ species.

“Sub-ns programming is allowed by strong ionic-hopping barrier reduction over a short insulating gap,” the authors said, claiming to show “a complete picture of conductance and switching phenomenology in the entire operation range.”

The Samsung Advanced Institute of Technology will describe a triple-layered TaOx RRAM aimed at storage-class memory applications. Multi-level cell (MLC) RRAMs were fabricated using a triple-layer structure (base layer/oxygen exchange layer/barrier layer), achieving a reproducible multi-level switching behavior.

A new programming algorithm was developed for more reliable and uniform MLC operation. “As a result, more than 10^-7 cycles of switching endurance and 10 years of data retention at 85°C for all the 2 bits per cell operation were achieved,” the authors reported in the paper’s abstract.

Panasonic researchers will describe their efforts to scale the conductive filament of TaOx bipolar ReRAMs. The effort sought to achieve long retention times with low current operation. “We demonstrate for the first time that the density of oxygen vacancy in a conductive filament plays a key role in ensuring data retention.”

The authors said they will show “very good retention results” of up to 100 hours at 150˚C even under low current operation.

Tags: GlobalFoundries, Hynix, Imec, Intel, ReRAMs, Samsung, STT-RAM

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