By Mark LaPedus

The technology roadmap for semiconductors remains in flux, as there are more signs that the foundries may accelerate the insertion point for finFET transistors amid next-generation lithography delays.

Even before finFETs, there are also questions about the 20nm node at the foundries. And at a recent event, various factions debated over which technology will enable future designs. In general, the two main technology candidates are based on bulk CMOS and silicon-on-insulator (SOI). Startup SuVolta Inc. has developed another option. And 2.5D/3D stacked technology provides yet another scaling path.

Causing part of the confusion in the semiconductor roadmap is the exact timing for the insertion point of extreme ultraviolet (EUV) lithography. Right now, the foundries plan to use 193nm immersion lithography and double-patterning to enable planar devices at 20nm.

If EUV is ready, the foundries hope to move into finFET production at 14nm. But if EUV is late at 14nm, the foundries will use triple-patterning at that node, said Shang-yi Chiang, executive vice president and co-chief operating officer at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), at the company’s recent technology symposium.

Another option is to accelerate the insertion point for finFETs, which could be introduced at a new half-node — perhaps 18nm or 16nm, he said. This would be done with 193nm immersion and perhaps double-patterning. Asked if TSMC has changed its current finFET roadmap for the 14nm node, Chaing told SemiMD: “Not at this moment.”

At a separate event, Joël Hartmann, corporate vice president of front-end manufacturing and process R&D at STMicroelectronics Inc., put it more bluntly. “At 14nm, we want EUV,” Hartmann said during a presentation at last week’s GSA Silicon Summit in Mountain View, Calif. “The industry absolutely needs EUV. The problem is that EUV is late.”

If EUV remains late at 14nm, Hartmann also proposed the idea of pulling in the roadmap and rolling out finFETs at the 16nm half-node. Nvidia, Qualcomm and others are also nudging their foundry partners to accelerate their respective finFET production schedules.

Much of this largely depends upon ASML Holding NV’s ability to ship EUV. Last week, ASML disclosed its initial production EUV tool – the NXE:3300B – will ship by year’s end, as promised. The main problem still centers around the EUV light source. The main source vendor, Cymer Inc., claims to have demonstrated 30 Watts of power at a high duty cycle. Cymer also demonstrated 50 Watts of raw power, applying pre-pulse technology. But to achieve acceptable throughputs of 60 and 125 wafers an hour, the power source must hit 100 Watts and 250 Watts, respectively.

20nm questions

While EUV remains a question mark, there is also some debate regarding the technology roadmap for semiconductors. First, there are some major questions surrounding the 20nm node in general. As reported, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) recently said it plans to combine technologies and offer one process at the 20nm node.

“The argument is that the R&D requirements to do (multiple process) variants is just too great to pull off for 20nm,” said G. Dan Hutcheson, president of VLSI Research Inc. “Another argument is that variability is so high that it swamps the electrical distinctions between” the various variants.

”Given (the advent of) multi-core architecture, it makes sense that designers would want to use both high-performance and low-power processes with different transistors for different cores on the same chip,” Hutcheson said. “There have always been different transistors on the same chip anyway, just not on this scale. Hence, there would only be a need for a single process, but with multiple modules to address (various process) needs.”

He added: ”You still have the same variability problem, but having a version makes it easier to manage on the fab line as well as in the end market. Designers would love this and designers always get what they want. Thus, I would argue that a single process strategy at 20nm is not only a trend, but the new normal.”

On the transistor front, meanwhile, Intel Corp. has moved into production with bulk-based finFETs at 22nm, with plans to extend that technology down to future nodes. Outside of Intel, the two options for the 28nm and 20nm nodes include bulk planar transistors and fully-depleted silicon-on-insulator (FD-SOI). At 14nm, planar transistors are expected to run out of steam, requiring either bulk finFETs or SOI-based finFETs. SuVolta has proposed another technology.

Bulk vs. SOI vs. SuVolta

The three basic camps — bulk, SOI and SuVolta — each claim they have a superior solution. But all camps agree on one premise. “Clearly, the end-user doesn’t want” less performance, said Paul Boudre, chief operating officer at SOI wafer specialist Soitec, during a panel discussion at the GSA event. “The end-user wants more.”

Regarding the direction of transistor technology, Boudre said: “Bulk is running out of gas at 20nm.” For decades, CMOS circuitry has been implemented on standard bulk silicon wafers. The advantage of bulk CMOS is cost, flexibility and scalability, but the SOI camp has a different viewpoint.

At the GSA panel, Matt Crowley, vice president of hardware at FPGA startup Tabula Inc., represented the bulk camp. Recently, Tabula made headlines, when the startup struck a foundry alliance with Intel. Intel will make Tabula’s FPGAs based on its 22nm tri-gate and bulk process.

In Intel’s tri-gate structure, the traditional “flat” two-dimensional planar gate is replaced with a thin 3D silicon fin that rises up vertically from the silicon substrate. Intel claims that its tri-gate transistor provide up to 37 percent performance increase at low voltage versus Intel’s 32nm planar transistors.

Crowley said Tabula is bullish about Intel’s tri-gate technology, because it provides lower power for FGPAs. “The finFET enables traditional scaling,” he told SemiMD. “The finFET is compatible with our CAD infrastructure.”

The rival SOI camp both agreed and disagreed. The SOI camp agreed that the world is moving towards fully-depleted finFETs, but disagreed that bulk is the way to go. “SOI is vastly superior” over bulk for finFETs, said Subramanian Iyer, IBM Fellow and chief technologist at IBM Corp.’s Microelectronics Division, during a presentation at the GSA event.

Iyer said bulk-based finFETs are susceptible to junction leakage and “fin height variability.” For finFETs in general, there is a perception that it is difficult to control the widths and heights of the fins in the manufacturing process.

IBM, one of the champions for SOI in the market, will move to finFETs on SOI wafers at the 14nm node. However, the Fishkill Alliance of companies, including Samsung, GlobalFoundries, Toshiba, and others, will pursue bulk finFETs at the 14nm node.

For years, AMD, IBM, and Freescale have been among the largest-volume users of SOI wafers. SOI wafers command a price premium over bulk, but Soitec has argued that by using the buried oxide layer, the number of process steps can be sharply reduced, with about 90 fewer total steps. Shallow trench isolation steps can be largely eliminated, for example.

Propelling the technology for future designs, Soitec recently said it is ready to provide SOI wafers to both planar (FD-2D) and finFET (FD-3D) customers. STMicroelectronics recently announced they will pursue fully-depleted SOI (FD-SOI) for 28nm application processors.

Planar FD-SOI technology relies on an ultra-thin layer of silicon over a buried oxide. Compared to bulk, FD-SOI has 10 percent fewer process steps and the wafer costs are roughly equal, ST’s Hartmann insisted. STMicroelectronics also plans to use FD-SOI at the 20nm node, he said.

Meanwhile, SuVolta presents another option. SuVolta’s so-called Deeply Depleted Channel (DDC) transistor technology is said to leverage existing CMOS design rules and process flows, and can be manufactured in existing fabs because it does not require new equipment or new materials.

During the GSA panel, Pushkar Ranade, senior director of process integration at SuVolta, also floated an idea that emerges from time to time: Let’s slow down the two-year process technology cycle in order to get a return-on-investment. “Is a two-year cadence the right cadence? Maybe a four-year — or five-year — cadence makes sense,” he said. “The industry could have a longer cadence, but improve the feature” sets of each technology node.

For example, the current versions of Apple Inc.’s successful iPad are based on a 45nm application processor – at a time when the industry is hyping 14nm, he added.

Tags: ASML, Cymer, IBM, Intel, Soitec, STMicroelectronics, SuVolta, TSMC

This entry was posted on Sunday, April 29th, 2012 at 4:54 pm and is filed under News Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.