By Mark LaPedus

For years, the analog and mixed-signal industry has been talking about the need for a standard and interoperable process design kit (PDK) to reduce costs and speed up the design cycles in a foundry. But to date, the advent of a single and standard PDK remains elusive, as various factions still agree to disagree about the future of the technology.

A PDK is a set of foundry-verified data files, component building blocks and process recipes used in an analog and mixed-signal design flow. The foundries must develop, support and maintain new and proprietary PDKs for each and every process technology and tool set. This in turn is becoming too costly for the foundries and seen as a major bottleneck in custom design.

Over the years, a large percentage of analog and mixed-signal designers use proprietary EDA tools and associated PDKs from the dominate supplier in the area: Cadence Design Systems Inc. Other EDA houses also compete with tools on the analog/mixed-signal front.

But one industry group — the Interoperable PDK Libraries Alliance or IPL Alliance — has taken steps to drive a rival and interoperable PDK standard. And at the upcoming Design Automation Conference (DAC) in San Francisco, the IPL Alliance is expected to announce an updated version of its PDK standard – dubbed IPL 2.0, which will support 40nm designs.

Still another group, the OpenPDK Coalition, has been developing a PDK standard at the 22nm/20nm node. That’s the good news. The bad news? For the foreseeable future, foundries must still support multiple and proprietary PDKs. Some say there is no need for a new standard, because designers are already happy with existing tools.

All agree that standards are important in the electronics industry. But the problem is that sometimes a new standard supports a technology that is different — and not necessarily better — than the status quo. “The foundries want (a standard PDK) more than anybody,” said Andy Brotman, vice president of design infrastructure at silicon foundry vendor GlobalFoundries Inc. The trouble is that “if you write to a single standard, the (individual) tools might not be the optimal solution.”

David Abercrombie, program manager for Advanced Physical Verification Methodology at Mentor Graphics Corp., said that developing a new standard for PDKs is easier said than done. “There are several challenges,” he said. “There is a legacy technology and change is always difficult.”

The issue is that vendors like Mentor must look at all standards. “We support everything,” he said, “because there is no single standard that has mindshare.”

PDK wars

Unlike the digital, analog design is a slow and manual process. For years, this market has been dominated by Cadence and its Virtuoso tool environment. The parameterized cell (p-cell) libraries within Virtuoso are written in a proprietary language called Skill.

Other EDA vendors sell rival schematic-layout analog tools, which use Skill or another language. The tools from vendors do not interoperate and require translators to talk to one another. The foundries must support the associated PDKs, which are also proprietary and interoperable.

Over the years, there have been several attempts among EDA vendors to develop a standard and interoperable PDK to reduce costs and speed up designs. The most ambitious effort to develop an open PDK — and break Cadence’s stranglehold in custom EDA tools — emerged in 2007, when the IPL Alliance was formed.

The founding members were AWR, Ciranova, SpringSoft, Silicon Navigator and Synopsys. Synopsys was (and still is) leading the charge in IPL. To date, IPL has 18 members, including Altera, Dongbu, Mentor, STMicroelectronics, TowerJazz, TSMC and Xilinx.

Missing from the group is Cadence, which has been reluctant to endorse IPL and for good reason: It competes against Virtuoso. In 2010, the IPL Alliance released the industry’s first open standard for interoperable PDKs. Geared for 90nm designs and built around the OpenAccess database, the so-called iPDK from IPL is based upon Ciranova’s PyCell technology, which itself uses a rival programming language called Python.  The so-called IPL1.0 reference kit included a developer’s guide, a sample 90nm reference iPDK and user guide.

At this year’s DAC, the IPL Alliance will roll out the next version, which supports 40nm designs, said Jingwen Yuan, president of IPL Alliance, who is also strategic alliance manager at Synopsys.  “Over the past three years, we’ve seen a strong adoption for iPDK,” Yuan said. “If you look at iPDK, the benefits are very clear.”

In the past, each foundry had to create specialized PDKs for each and every EDA vendor. In contrast, semiconductor foundries and integrated device manufacturers (IDMs) can use this standard to build a single iPDK that works with multiple OpenAccess-based custom design tools. The iPDK will enable development teams to only develop a single PDK for each process node, reducing development costs, shortening delivery schedules and providing designers earlier access to new advanced process technologies across multiple tools, Yuan said.

Despite the call for standards, the foundries still develop and maintain multiple PDKs. For example, GlobalFoundries belongs to IBM Corp.’s Common Platform alliance. IBM and Samsung Electronics Co. Ltd. are also members. The Common Platform group itself has a single PDK, GlobalFoundries’ Brotman said. But each member of the group separately tweaks that PDK into their own customized version, he said.

On its Web site, GlobalFoundries says its PDK is based on the Virtuoso analog design environment from Cadence. At least publically, GlobalFoundries has also endorsed IPL’s iPDK technology.

Rival Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is a big supporter of IPL, but the foundry giant also remains tied to Cadence. TSMC supports a PDK based on the technology from IPL, which includes a “patch” that supports Cadence’s Skill language, said Tom Quan, Open Innovation Platform marketing manager with TSMC.

Universal PDK?

The industry hopes to solve the problem, when the market moves towards the OpenPDK technology at the 22nm/20nm node. In 2010, Si2 led the charge to form the OpenPDK Coalition. There are 13 companies in the coalition: Agilent, AnaGlobe, Cadence, GlobalFoundries, IBM, Intel, Mentor,   NXP, Samsung, Silvaco, SpringSoft, STMicroelectronics and Synopsys.

TMSC is not part of the group, but the foundry giant is a member of Si2. The goal of the OpenPDK Coalition is to define open standards for a universal PDK structure that will be portable across foundries and agnostic to EDA tools. It will provide interoperability with  proprietary formats and languages, such as Skill,  CDF, Hspice, Spectre, SVRF and others.

Based on OpenAccess, OpenPDK incorporates an ”abstraction layer” or translator. In other words, OpenPDK is a front-end that will support PDKs from Cadence, IPL and others, but it will require translators for tools to communicate from one tool to another.

Some believe the effort is far too ambitious and will create just another competitive iPDK for the foundries to deal with. IPL’s Yuan said OpenPDK is a more IDM-driven technology that is  complementary – rather than competitive – to the efforts from the IPL. “We’re complementary,” she said. “OpenPDK is focused on interoperability and implementation.”

Others say that many of the technologies can be integrated in a single PDK. “Spice models are pretty portable,” said GlobalFoundries’ Brotman. “There are some things that can be common,” but in PDKs, “there is some customization that needs to be done.”

According to Si2, the OpenPDK specifications have been finalized and are currently under review. According to Si2: “OpenPDK consists of several specs that are in different stages of development, some of which are developed in the OpenPDK Coalition and some of which are independently developed to support design for Manufacturability (DFM) by the DFM Coalition.” So, the status is as follows:

—OpenDFM 1.2 (including Targeting): Released and specs are available.
—OPEX (for Open Parasitic Exchange Format): Has not yet entered it’s 60-day exclusion period and
will not likely be released by DAC.
—OPDK Symbols (updated version of Analog Symbol Library): Currently in the 60-day exclusion period, specs expected to be released before DAC (target: 06/01/2012).
—OPDK Callbacks and Parameters: Currently in the 60-day exclusion period, specs expected to be released before DAC (target: 06/01/2012).

Tags: Cadence, GlobalFoundries, IBM, Intel, Mentor, Synopsys, TSMC

This entry was posted on Wednesday, April 25th, 2012 at 4:25 pm and is filed under News Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.