Memoir Rolls ‘Algorithmic’ Embedded Memory IP
By Mark LaPedus
In what could lower systems cost and jumpstart SRAM scaling, intellectual-property (IP) chip startup Memoir Systems Inc. has rolled out its first product — a new class of “algorithmic” embedded memory technology.
Memoir’s IP, dubbed Renaissance 2X, is basically a 2-port, 6-transistor SRAM (6T-SRAM) bit cell for embedded memory applications. Like rival technologies, Memoir’s IP can perform a read and write operation. “It is portable to any design rule or process technology,” said Adam Kablanian, chief executive of Memoir, based in Santa Clara, Calif.
But unlike other technologies in the market, Renaissance 2X is said to incorporate an additional “dual-port” capability as part of a “super-set” scheme within the IP. The technology is scalable by at least a factor of 10X, enabling the development of multi-port memories for use in SRAM scaling.
Renaissance 2X also uses what Memoir calls Algorithmic Memory. Implemented at the RTL level, this technology uses proprietary algorithms to enable multiple embedded memory interfaces simultaneously and on-the-fly.
A chip designer still sees a traditional 6T-SRAM scheme as the interface. But unlike competing IP, Renaissance 2X can be configured to handle four separate memory generators or options: a 2-port one-read/one-write (1R1W) operation; a dual-port two-read/write (2RW) operation; and specialty memories for two-read or one-write (2Ror1W) and one-read-write/one-write (1RW1W) operations.
“Memoir’s overall vision with our Renaissance product family is to bring new life and an innovative approach to embedded memory design and development across the industry,” Kablanian said.
One analyst was impressed. “Speed is one key challenge for a lot of embedded systems, especially those dealing with signal processing or lookup,” said Jim Handy, an analyst with Objective-Analysis, a research firm. “Memoir’s approach is an elegant solution to some of these problems. Memoir removes the need to ‘brute force’ the design using high power or aggressive process technologies when a clever architecture can provide similar speed.”
Memoir's IP enables various operations on the fly (Source: Company)
Startup’s memoir
Memoir Systems was co‐founded in 2009 by Sundar Iyer and Da Chuang. The startup is backed by Lightspeed Venture Partners. Iyer, chief technology officer for Memoir, was previously the co‐founder and CTO of Nemo Systems, a networking memory company that was acquired by Cisco Systems. Chuang, chief operating officer of Memoir, was a technical leader at Cisco.
In conjunction with the formal launch of the company last October, Kablanian was named as CEO of Memoir. He was the co-founder of Virage Logic and served as president and CEO of the memory IP house until 2007. He was chairman of Virage until 2008. Not long ago, Virage was acquired Synopsys.
Memoir Systems competes — and can work in conjunction — with various providers of embedded SRAM. ARM, Dolphin, Synposys and others provide embedded SRAM IP. GlobalFoundries, TSMC, UMC and other foundries provide similar IP. And various chip makers develop their own embedded memory.
“A key part of our strategy is to work with foundries, IDMs, library vendors, and third-party IP suppliers to make our technology available such that it sets a new standard on how memory products are developed,” Kablanian added.
Memoir claims that today’s embedded memory technology is a limiting factor in systems design. For example, networking switches are finding it harder to process incoming packets fast enough to avoid overruns. In another example, high-speed multicore processors are changing the landscape in desktops and servers. But processors can stall under heavy workloads due to contention over shared memory resources such as L2 or L3 caches.
There are several options for embedded memory in designs. Embedded DRAM is cheap, but there are latency issues. SRAM is faster than DRAM and is typically used for cache applications in processors. The problem with SRAM is that it “is not scaling,” said Badawi Dweik, director of product marketing at Memoir
At 40nm, for example, embedded SRAM operated at speeds of up to 800-MHz, Dweik said. Then, at 28nm, embedded SRAM moved up to speeds of 1-GHz. “At 20nm, that line becomes flat” at 1-GHz, he said.
To continue embedded SRAM scaling at 20nm and beyond, Memoir proposes the idea of using multi-port memories in designs. Rather than brute-force scaling, “we can add more ports,” he said. “The best (part of our IP) is that we can add more ports.”
The company is rolling out a dual-port technology, but it claims to have already shipped IP with up to 10 ports. Today, embedded SRAM is offered in 1T, 6T and 8T configurations. Renaissance 2X offers up to 30 percent increased clock speeds and up to 50 percent area and power savings over comparable physical memory compilers, according to the company.
Renaissance 2X is said to eliminate the need to build multiple variants of dual-port and 2-port physical compilers based on the conventional 8-transistor (8T-SRAM) memory bit cells for new process nodes. In fact, traditional dual-port and 2-port memories require specialized 8-transistor bit cells. This requires extra effort to develop an additional set of physical compilers, according to Memoir.
Renaissance 2X Generators are available now and list pricing starts at $250,000 plus royalties.
