Berkeley’s Hu Tips Industry Standard Model for finFETs
By Mark LaPedus
During the Synopsys Users Group Conference (SNUG) in Santa Clara, Calif. on Wednesday (March 28), UC Berkeley Professor Chenming Calvin Hu disclosed that his group has officially released the first industry standard transistor model for multi-gate structures or finFETs.
Led by Hu and others, the Berkeley Short-channel IGFET Model Group — or BSIM — has officially released BSIMCMG106.0.0, the first standard compact model for FinFETs. The release — better known as BSIMCommon-Gate Multi-Gate (BSIM-CMG) — has been developed to model the electrical characteristics of multi-gate structures or finFETs. The group has released the source code, QA test results and related materials for the technology on its Web site for free.
The move will bring finFET transistors a step closer to production within the leading-edge foundries, said Hu, a pioneer in finFET research and the TSMC Distinguished Professor in the Department of Electrical Engineering at the University of California at Berkeley (UCB).
Intel Corp. has already moved finFETs — of which it calls tri-gate — into production at the 22nm node, reportedly based on its own models. Meanwhile, the leading-edge foundries, including GlobalFoundries, Samsung, TSMC and UMC, are racing each other to develop finFETs for the 14nm node.
The advent of BSIM-CMG is a “big deal” for the foundries, Hu told SemiMD after his presentation at SNUG. With the technology, “the foundries can now issue the models for their customers.”
According to the UC Berkeley Web site, Hu is considered the “father of 3D transistors” for leading the development of finFETs with several others back in 1999. From 2001 to 2004, he was the chief technology officer at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC).
Located in the Department of Electrical Engineering and Computer Sciences (EECS) at the UC Berkeley, BSIM develops MOSFET SPICE or compact models for circuit simulation and chip development. SPICE is a general-purpose simulator, which predicts the behavior of a design. A compact model reproduces or models the transistor characteristics in SPICE simulation.
The compact model developments are charted by the Compact Model Council (CMC), a consortium of semiconductor companies and simulator vendors that promotes BSIM as the industry standard compact model. CMC was formed in 1996, when the industry had dozens of proprietary SPICE models.
Berkeley's model supports various finFET structures (Source: UCB)
Challenges seen on the horizon
During his presentation at SNUG, Hu said the industry faces several challenges, including the shift to multi-patterning and the availability of extreme ultraviolet (EUV) lithography. “It would be nice to have” EUV, he said. “It would be nice if the price was lower.”
He also warned that today’s planar transistors are running on its last legs. In device scaling, planar transistors have or will begin to experience short-channel effects and other problems, meaning the industry must embrace a new transistor structure.
The candidates include finFETs and fully depleted silicon-on-insulator (FD-SOI). Startup SuVolta Inc. has emerged and developed another option, dubbed Deeply Depleted Channel (DDC) transistor technology.
“Today, we have a choice” for next-generation transistors, Hu said during the presentation. In the finFET camp, “Intel has a put a lot of momentum behind it.”
There are some advantages with FD-SOI, which is backed by IBM Corp. “It doesn’t take as much investment in the fab,” he said. “The investment has been made by Soitec.”
During a question and answer session, Hu was asked to comment on on SuVolta’s technology. “It’s an enhancement,” he said, without elaborating.
Right now, the foundries are pushing hard for finFETs at 14nm. Hu declined to comment if the foundries are accelerating their finFET efforts and would insert the technology at the 20nm node. He didn’t believe the foundries would have difficulties in bringing up finFETs at 14nm, given the fact that TSMC and others have been working on the technology for several years.
The ability to obtain a compact transistor model for finFETs will help the cause for the foundries. In the works for some time, BSIM-CMG “is implemented in Verilog-A,” according to BSIM. “All the important multi-gate (MG) transistor behaviors are captured by this model.”
Bulk CMOS, however, is not going away anytime soon. For some time, the BSIM group has promoted so-called BSIM6 technology as the new bulk MOSFET model. BSIM6 is the follow-on to BSIM4, which appeared several years ago. “The model development was done from scratch where new expressions for charges were derived,” according to BSIM. “The model has been developed to provide source-drain symmetry and correct harmonics behavior for RF circuit simulation. BSIM6 model is undergoing stringent quality assurance tests to demonstrate its capability for mixed-signal/RF design.”
BSIM6 model is under evaluation for standardization at the CMC. The modeling groups at UCB and École Polytechnique Fédérale de Lausanne (EPFL) have agreed to collaborate on the long-term development and support of BSIM6 as an open-source MOSFET SPICE model for worldwide use.
March 31st, 2012 at 8:41 pm
If I had known it would be published here I would have spent more time creating better figures