ST-Ericsson Adopts FD-SOI for Mobile Products
By David Lammers
Soitec (Bernin, France) announced that ST-Ericsson will use planar fully depleted silicon on insulator (FD-SOI) technology in future mobile platforms, including the NovaThor SoCs used in smart phones. Compared with conventional bulk CMOS, 28nm FD-SOI technology provides 35 percent lower power consumption at maximum performance, resulting in mobile systems with four additional hours of Web browsing or as much as a day of additional battery life, Soitec said.
ST-Ericsson has delivered its NovaThor mobile platform solutions to Nvidia and other smart phone providers. Louis Tannyeres, chief chip architect at ST-Ericsson, said “together with innovations in overall platform system design, advances in process technology are key to delivering next-level performance and higher power efficiency. The results of our work with STMicroelectronics on FD-SOI have demonstrated that this technology is able to deliver these benefits in a cost-effective manner, while allowing us to differentiate our solutions.”
Soitec COO Paul Boudre said ST-Ericsson’s decision represents the industry’s “first step toward fully depleted planar CMOS technology, years ahead of when alternative processes will be available from foundries.”
FD-SOI allows semiconductor vendors to deliver power and performance advantages similar to those achieved with vertical, finFET transistors, with less manufacturing complexity. While foundries have plans to move to finFETs at the 14nm node, the FD-SOI technology is available now, at the 28nm generation, with minimal design changes from bulk CMOS technology.
With wafer production facilities in Bernin, France, and Singapore, Boudre said Soitec can meet the high-volume SOI wafer needs of the mobile market. To support fully depleted technology, the active silicon layer must be kept to 10 nm or less, on top of a thicker buried oxide layer which prevents current from leaking out. Other wafer manufacturers, including MEMC and SEH, have licensed Soitec’s Smart Cut technique for creating the SOI wafers.
Processors built on a fully depleted SOI technology can achieve 60 percent higher peak performance. Relatively high performance also is possible at very low operating voltages in the sub-0.7V regime, he said.
STMicroelectronics said at the International Electron Devices Meeting (IEDM) last December that it is implementing mobile applications processors in a FD-SOI technology, using 28nm design rules. It has developed back bias techniques which allow the chip to switch between power-saving and performance modes which are not available with FinFETs.
Joël Hartmann, STMicroelectronics assistant general manager of technology R&D, said STMicroelectronics and partners Leti, Soitec and IBM have invested several years of development in FD-SOI technology. “ST has recently demonstrated the strong differentiation of this technology versus conventional bulk CMOS, both for high-performance and low-power features on several IPs at 28nm and below,” Hartmann said.
(Source: Symposium on VLSI Technology).
Tags: FD-SOI, Leti, SOI, Soitec, ST-Ericsson, STMicroelectronics