Semiconductor Manufacturing Research News
An MIT group has developed a software simulator, Hornet, that models the performance of multicore chips much more accurately than previous simulators. A new version of Hornet factors in power consumption, patterns of communication between cores, processing times of individual tasks, and memory-access patterns.
MIT reported that at the Network-on-Chip Symposium, Myong Hyon Cho, a PhD student in the Department of Electrical Engineering and Computer Science (EECS) and his colleagues analyzed a promising multicore-computing technique in which the chip passes computational tasks to the cores storing the pertinent data rather than passing data to the cores performing the pertinent tasks.
Hornet identified the risk of a problem which other simulators had missed called deadlock, a situation in which some number of cores are waiting for resources — communications channels or memory locations — in use by other cores.
Nanowire Composition
An MIT-led team said it is able to control the size and composition of individual indium gallium nitride (InGaN) nanowires by adjusting the amount of gases used while growing the nanowires.
In a paper published in Nano Letters, Georg Haberfehlner of CEA-Leti, and Sung Keun Lim, Sam Crawford, and Silvija Gradeča, in the MIT department of materials science and engineering, said they were able to tune the seed particle saturation and size via the supply of III and V sources during the growth steps.
The MIT team said the full potential of nanowires depends “on the ability to control nanowire structure, composition, and size with high accuracy.”
“Our approach can be applied to other materials systems and provides a foundation for future development of complex nanowire structures with enhanced functionality,” the researchers said.
Researchers are learning to control the size and composition of InGaAs nanowires. (Source: MIT)
Fault-tolerant Implantable Devices
An EU project named Desyre has applied fault-tolerant techniques — building a reliable system on unreliable components — to the chipsets used in pacemakers, deep brain stimulators that treat Parkinson’s disease, and other implantable medical devices.
(Source: EU)
Ioannis Sourdis, an assistant professor in computer engineering at Chalmers and the project leader of DeSyRe (on-Demand System Reliability), said the fault-tolerant approaches could improve reliability while at the same time reducing power and performance overheads associated with fault-tolerance.
The Desyre consortium separates the System-on-Chip (SoC) into circuits extremely resistant to faults, and other fault-prone processing cores. The fault-free part of the chip is responsible for monitoring the operation of the fault-prone part.
– by David Lammers
Tags: fault tolerant computing, MIT, nanowires, simulators