Applied, IME Open $100M 3D Chip Lab in Singapore
By Mark LaPedus, SemiMD senior editor
Expanding its respective efforts in a hot area, Applied Materials Inc. and the Institute of Microelectronics (IME) have officially opened a 3D chip lab in Singapore at a combined investment of over $100 million.
Applied and Singapore’s IME, a research institute under the Agency for Science, Technology and Research (A*STAR), opened the Centre of Excellence in Advanced Packaging at Singapore’s Science Park II.
In April of 2011, Applied and IME originally announced the research collaboration for advanced packaging in Singapore. As part of the grand opening, announced Wednesday (March 7), Applied said the lab will combine Applied’s equipment and process technology with IME’s research capability in 3D chip packaging. Research activities are already underway with a team of over 50 personnel.
The facility features a 14,000 square foot Class-10 cleanroom and is equipped with an integrated line of 300mm manufacturing systems to support the research and development of 3D chip packaging using through-silicon vias (TSVs). The facility will also allow both parties to pursue independent research initiatives, including process engineering, integration and hardware development.
“Today, we are not only opening the most advanced wafer level packaging lab of its kind in the world, but we are also opening a new product development capability for Applied Materials in Asia,” said Mike Splinter, chairman and chief executive of Applied Materials. “This center will strengthen our ability to advance new technologies and allow us to work more closely with our customers in Asia.”
Applied has a strong presence in Singapore. In 2010, Applied opened its Singapore Operations Center, Applied’s first facility in Asia for manufacturing its advanced semiconductor equipment. The 32,000-square-meter center, located in the Changi North Industrial Park, serves as a hub for Applied’s semiconductor equipment manufacturing around the world, as well as support its worldwide supply chain operations and other corporate functions.
In addition, Applied is a major player in the 3D TSV equipment arena. There are a number of process steps to make a 3D chip. In the via creation or via processing process, there are five main manufacturing steps: etch, chemical-vapor deposition, physical-vapor deposition, electroplating, and chemical mechanical polishing. Applied has an tool offering in these and other segments.
Asked if vertical or 3D memories will boost Applied’s sales, Splinter during a recent conference call said vertical NAND devices will provide the NAND vendors with a renewed ability to cut costs and stay ahead of Moore’s Law. But he said vertical NAND products “are still a few years away.”
For 3D and other areas, Splinter recently said collaboration across the ecosystem will need to be done earlier and at a deeper level. In another example, the Applied CEO recently said tool vendors want more say in the direction of 450mm technology.
Singapore expands in 3D
Meanwhile, Dim-Lee Kwong, executive director of IME, added, “This collaboration will enable the semiconductor industry to accelerate the adoption of 3D chip packaging.”
IME has other alliances in 3D. In 2009, IME launched a 3D chip consortium . The research collaboratively undertaken by members of the 3D TSV Consortium has been carried out in two 18-month phases. Phase one, which is led by IME, serves to establish TSV design and processes for 200mm and 300mm TSV wafer 3D IC assembly. Phase two will demonstrate the integration of functional mobile devices with TSV on a 300mm wafer process line.
Participating companies in phase one of the first 3D TSV Consortium that commenced in September 2009 include GlobalFoundries Singapore Pte. Ltd., STATS ChipPAC Ltd. and United Test and Assembly Center Ltd.
The 3D TSV Consortium is also supported by 3M, Asahi Glass Co. Ltd., Brewer Science Inc., HD Microsystems, Hitachi Chemical Co. Ltd., Nagase & Co. Ltd., Namics Corporation, Nitto Denko (Singapore) Pte. Ltd., OM Group Ultra Pure Chemicals, Sekisui Chemical Co. Ltd., Shanghai Sinyang Semiconductor Materials Co. Ltd., Sumitomo Bakelite Co. Ltd., The Dow Chemical Company and Thin Materials AG.
Late last year, IME and Tezzaron Semiconductor announced a research collaboration agreement to develop through silicon interposer (TSI) technology. Initial production devices are already in development, based on IME’s TSI technology and incorporating 3D-ICs from Tezzaron. Fabrication will be completed in IME’s 300mm R&D Fab. Tezzaron is having its 3D devices made on a foundry basis by GlobalFoundries.
Tags: 3M, Applied, Brewer, GlobalFoundries, IME, STATS, United Test and Assembly Center Ltd.