Semiconductor Manufacturing Research News
Intel Describes NTV Test Chips at ISSCC
Researchers working at Intel Labs went to the International Solid State Circuits Conference (ISSCC), going on this week in San Francisco, to describe progress in near-threshold voltage (NTV) technology.
Near threshold voltage (NTV) operation reduces power consumption. (Source: Intel)
Intel Labs director David Perlmutter, in an ISSCC keynote speech Monday (Feb. 20), described an Intel Architecture test processor, code-named Claremont. Initially demonstrated last year, Intel described the chip layout and design methodology, and said it now uses an NTV approach for all of the compute functions. Built in a 32nm SoC technology, Claremont operates from 280mV @3MHz to 1.2V @915MHz, and the energy efficiency is 4.7x better in NTV mode. It consumes only 2 mW at minimum power consumption.
Also at ISSCC, Intel gave the first demonstration of NTV technology on its 22nm tri-gate technology, describing the operation of a SIMD block which performs as the Vector Permutation Engine of a graphics processor. The dynamic voltage was scaled down to 280mV for what Intel said is a 9x efficiency gain over conventional CMOS. Memory was also implemented, and Intel said the demonstration shows “NTV viability for both compute and memory.”
Bringing Optical Interconnects onto Silicon
Researchers based at the Massachusetts Institute of Technology are investigating two ways of incorporating optical interconnects – monolithic integration and 3D TSV connections — that could be used to connect many processor cores on future ICs.
MIT researchers are working with IBM to build the optical components on the same die, including the photodetectors and waveguides, controlled by on-chip circuitry. The IBM fab can’t handle one step: etching a channel under the waveguides, to prevent light from leaking out of them. And for now, the laser is an off-chip component, though eventually on-chip lasers could be used to connect hundreds of cores.
Monolithic optical interconnects would be ideal for mobile devices. (Source: MIT)
MIT researcher Vladimir Stojanovic said the uncertain future of transistor design may provide an opening for on-chip optical interconnects, which use less power than conventional interconnections. As MPU designers face other changes to logic transistors, they might be more open to adding optical to the mix. “That’s the moment it has to come in,” Stojanovic said, “at the moment where everything’s in flux, and soft.”
Another team led by Michael Watts, is working at MIT’s Lincoln Laboratory to integrate optical and electrical components which are built on different wafers and connected with TSVs.
Organic Package Supports Thin Die Stacking
Georgia Tech’s Packaging Research Center described a 3D organic package at 130um thickness with a 30um interconnection pitch.
The “Ultra-Slim” packages have built-in vertical connections to the top surface, supporting package- on -package stacking of thin silicon and GaAs devices. The chip-last integration scheme allows RF passive components to be embedded into the substrate layers.
– By David Lammers
Tags: George Tech, Intel, M.I.T., near threshold voltage, NTV, optical interconnects, organic packaging