By Ed Sperling

The race to the next node on the Moore’s Law road map is going to be a lot bumpier than previous nodes, particularly in the design for manufacturing world.

The tools that worked at 28nm will need major tweaks at 20nm and beyond. To begin with, the delay in providing an acceptable power source for extreme ultraviolet lithography has created a number of alternatives—and each of them may require a different approach.

Case in point: LELE vs. SADP. LELE, also known as Litho-Etch-Litho-Etch, has been adopted by TSMC, while the Common Platform—IBM, GlobalFoundries and Samsung—are focused on SADP, or Self-Aligned Double Patterning. LELE uses two litho exposures to etch onto a mask, while SAPD adds a spacer layer. Both approaches work, despite the arguments back and forth about which one is better and why. But for DFM tools vendors, the challenge isn’t supporting one or the other. It’s supporting both.

“We don’t have a choice,” said Jean-Marie Brunet, director of product marketing for model-based DFM and place and route integration at Mentor Graphics. “We need to support all of them.”

In some cases, that includes both in one design, as STMicroelectronics is doing. A design engineer at the company displayed the so-called “two-color” approach at the SPIE Advanced Lithography conference in San Jose this week.

But if EUV isn’t ready by the 14nm node, most engineers believe they will have use triple patterning—splitting the mask into three parts. The problem there, according to Brunet, is that there is no way to have density balance among the three masks. He said that could make it far more difficult to automate the steps, leaving designers to do at least some of the design by hand.

Triple patterning adds another level of complexity, and it will require an almost complete rewrite of DFM tools to be able to provide that multi-layer density balance. Luigi Capodieci, R&D fellow at GlobalFoundries, said triple patterning may never actually be implemented because of cost.

“Triple patterning makes for good paper,” he said. “But I’m not sure the solution is cost-effective. The UV gap needs to be filled by something. We are working on 14nm today and we see the challenges. A lot will have to be done with double patterning.”

Lars Liebmann, an IBM distinguished engineer, said his company has looked at what else could fill the gap if EUV never becomes commercially viable. He said the first place where double patterning runs out of steam is the fins on finFETs. He said a tight pitch is needed for the fins, and even at 14nm engineers are right up against the frequency doubling limit.

“The channel length is fixed and the device width is fixed,” Liebmann said. “We’ve tried sidewall on sidewall, but control is horrible.”

One alternative is self-assembly, which he noted is close to commercial viability. He said the limitation in the past is that an entire chip had to be done at one pitch. IBM has since gotten to the point where it can create different pitch regions on the chip. He said it now is a potential alternative approach if EUV doesn’t come through in time.

How DFM tools will deal with self-assembly is unknown at this point.

Tags: GlobalFoundries, IBM, Mentor Graphics, STMicroelectronics

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