http://semimd.com/blog/2012/02/08/wanted-3d-chip-testing-solutions-and-standards/ Deep Insights for Chip Builders Sat, 18 May 2013 00:59:32 +0000 hourly 1 http://wordpress.org/?v= http://semimd.com/blog/2012/02/08/wanted-3d-chip-testing-solutions-and-standards/#comment-17062 David Cutler Tue, 28 Feb 2012 20:54:51 +0000 http://semimd.com/?p=4578#comment-17062 The Xilinx device is hardly stacked die since the dies are mounted horizontally not vertically its more akin to a multi-chip module than stacked die. The only 'stacking' is loosely related to and confined to the interconnect between the die. The Xilinx device is hardly stacked die since the dies are mounted horizontally not vertically its more akin to a multi-chip module than stacked die. The only ‘stacking’ is loosely related to and confined to the interconnect between the die.

]]> http://semimd.com/blog/2012/02/08/wanted-3d-chip-testing-solutions-and-standards/#comment-16091 David Cutler Tue, 14 Feb 2012 00:41:18 +0000 http://semimd.com/?p=4578#comment-16091 Why is it that everyone seems to be looking for a external test solution when an internal test solution maybe the most effective answer especially for mixed signal+RF stacks. What if the internal testability is sufficiently augmented with BIST and loop-back BIST such that the test can be initiated by a custom JTAG command and the result read from the TDO. This access could be standardized such that each assembly equipment would have the JTAG access and the test initiated for each 3D level assembled. Now if the die at the base of the stack were an FPGA then this could be programmed for the tests needed by the stack at each stage (possibly again through the JTAG) and would be such that it is effectively independent of the contents of the stack. Putting all the testing on chip creating an 'on-chip diagnostic test OCDT' seems to be a less complex solution that offers several benefits.....not only for testing the stack but also could be used as an in application diagnostic.....and also the FPGA could be programmed to perform the activity required for High Temp Operating Life Burn-in testing for reliability purposes. Why is it that everyone seems to be looking for a external test solution when an internal test solution maybe the most effective answer especially for mixed signal+RF stacks. What if the internal testability is sufficiently augmented with BIST and loop-back BIST such that the test can be initiated by a custom JTAG command and the result read from the TDO. This access could be standardized such that each assembly equipment would have the JTAG access and the test initiated for each 3D level assembled. Now if the die at the base of the stack were an FPGA then this could be programmed for the tests needed by the stack at each stage (possibly again through the JTAG) and would be such that it is effectively independent of the contents of the stack. Putting all the testing on chip creating an ‘on-chip diagnostic test OCDT’ seems to be a less complex solution that offers several benefits…..not only for testing the stack but also could be used as an in application diagnostic…..and also the FPGA could be programmed to perform the activity required for High Temp Operating Life Burn-in testing for reliability purposes.

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